IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
apogc01 Power on Reset
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. apogc01 is a general purpose, power good detector. A power good signal (active high) is generated as long as the supply voltage at the VDDA pin lies within the 4.5V - 5.5V limits. When the supply voltage is beyond the either low

aporc01 Power on Reset
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is bellow the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay of few microse

aporc02 Power on Reset
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept high as long as the supply voltage is bellow the high threshold

aporc03 Power on Reset
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. aporc03 is a Power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept low as long as the supply voltage is bellow the threshold voltage. When the high

aporc01 Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay

aporc02 Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is b

aporc03 Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. aporc03 is a Power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is below the threshold v

aporc01_5v Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 5V aporc01_5v is a dynamic Power-on-Reset (POR) circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low.

aporc02_5v Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 5V aporc02_5v is a Power-on-Reset (POR) circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.

aporc03_5v Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 5V aporc03_5v is a Power-on-Reset (POR) circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

aporc01 Power on Reset
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low.

aporc02 Power on Reset
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 aporc02 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on both the rising and failing edge of the supply voltage. During power-on, POR outputs is kept high as long as the supply voltage is below the threshold voltage.

aporc03 Power on Reset
X-FAB
0.60 µm
XT06
Layout
Schematic
Analog Library

XT06 aporc03 is a Power-on-Rest circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept high as long as the supply voltage is below the high threshold.

aporc01_3v3 Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aporc01_3v3 is a dynamic power-on-reset circuit (POR). The cell is suitable for applicaitons where low consumption is important.

aporc02_3v3 Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aporc02_3v3 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.

aporc03_3v3 Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aporc03_3v3 is a Power-on-Rest circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

aporc03_5v Power on Reset
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V aporc03_5v is a power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

CM1412ae Power on Reset
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

2Low consumption Power-On Reset (POR) core. The core has a voltage sense (configurable 0.9V - 5.5V), an internal current bias circuit and two configurable assertion delays (default are > 1μs and > 20μs). A configurable hysteresis (default 100mV).

aporc02_1v8 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aporc02_1v8 is a Power-on-Reset circuit with hysteresis. Both high and low reset signals are available. Reset signals are generated on power-on and power-off transitions. 40mV (typ) hysteresis for safer operation.

aporc03_1v8 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aporc03_1v8 is a Power-on-Reset circuit with hysteresis. Both high and low reset signals are available. Reset signals are generated on power-on and power-off transitions. 35mV (typ) hysteresis for safer operation.

aporc02_3v3 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aporc02_3v3 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on power-on and power-off transitions. Both high and low (POR and PORB) reset signals are available.

aporc03_3v3 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aporc02_3v3 is a Power-on-Reset circuit. Reset signal are generated on power-on and power-off transitions. Both high and low (POR and PORB) reset signals are available.

IPMS_430 Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

Compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features:
- 16 bit Risc CPU
- 7 address modes for source operands
- several low power features

IPMS_16CXX Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

8 Bit Microprocessor. The core IPMS_16CXX is a 8-bit microcontroller compatible to PIC 16CXX-family from Microchip.

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol used in low cost automotive networks. It enables cost efficient bus communication for applications where the bandwidth of CAN is not required. Support of LIN specification 2.2A

IMMS SENT Transmitter Soft IP
IMMS GmbH
All Geometries
All Processes
PT
Verilog

Silicon-proven Verilog implementation of a flexible configurable SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. Up to 16-bit data from two independent sensors.

IPMS_CAN_FD Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

IPMS_CAN is a CAN bus controller that performs serial communication according to the CAN 2.0B and the CAN FD specification.It is compatible to ISO CAN FD andthe non-ISO (Bosch) CAN FD standard and has extended time stamp and time trigger capabilities.

TI-Manchester Transceiver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-Manchester is a dual data bus transceiver designed for receiving CMOS/TTL Manchester II data, converting it and transmitting through a stepup transformer to the data bus...

D17IP14 Transceiver
Desert Microtechnology
0.35 μm
XH035
PT
Layout
Schematic

D17IP14 is a low voltage differential signal (LVDS) receiver (RX) for digital video data transfer.  It adherers to LVDS standards.  It has a 400 ohm input impedance. It amplifies the input signals to CMOS levels, 0 to 3.3V. 

D17IP09 Transimpedance Amplifier
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP09 is an 8 channel bank of transimpedance amplifiers.  It has a programmable transimpedance gain.  It is internally compensated and supplies a virtual ground to both sink and source current at the input.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 331 to 360 out of 379

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