IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
ADC12b017kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XH018
PT
GDSII
Schematic

Cyclic single ADC, 12bit resolution, 17kSps, 0.5 LSB INL, 12bit ENOB, 50µW power consumption.

ADC12b054kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XH018
PT
GDSII
Schematic

Cyclic single ADC, 12bit resolution, 54kSps, 1.6 LSB INL, 10.5bit ENOB, 370µW power consumption

ADC16b013kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XH018
PT
GDSII
Schematic

Cyclic single ADC, 16bit resolution, 13kSps, 12.7 bit ENOB, 50µW power consumption

ADC12b020MS350nm ADC
Fraunhofer IIS/EAS
0.35 μm
XH035
PT
GDSII
Schematic

Pipelined ADC, 12bit resolution, 20MSps, 9.6 bit ENOB@2MSps, 9.2 bit ENOB@20MSps,  2 LSB INL, 125mW power consumption

TI-RF-CMP Comparators
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-CMP is a low power CMOS RF comparator with 4 ns propagation delay and latch function. ESD protection provided.

TI-RF-DRV Driver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-DRV is a fully differential RF driver for differential signal processing applications. Common-mode level of differential outputs is adjustable that allows to shift easily the input signals for driving single-supply ADCs. ESD protection provided.

TI-RF-MUX Multiplexer
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-MUX is a 4-to-1 RF multiplexer designed with an internal current feedback output amplifier whose gain can be adjusted externally. There is a possibility of optional usage of two 4-to-1 devices as one 8-to-1 multiplexer. ESD protection provided.

TI-RF-Switch Analogue Switches
Thesys-Intechna
0.35 μm
XH035
VS
GDSII
Schematic

The TI-RF-Switch is a broad-band dual SPDT analog switch containing two single-pole double-throw switches. Used CMOS technology provides high isolation and low insertion loss at frequencies up to 1 GHz.

TI-16PI/150M ADC
Thesys-Intechna
0.18 μm
XT018
VS
GDSII
Schematic

TI-16PI/150M is a dual-channel fully differential 16-bit ADC with pipelined architecture optimized for high dynamic performance at sample rates up to 180 MSPS.

TI-Manchester Transceiver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-Manchester is a dual data bus transceiver designed for receiving CMOS/TTL Manchester II data, converting it and transmitting through a stepup transformer to the data bus...

ADC12b040MS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XC018
XH018
MP
GDSII
Schematic

Pipeline ADC, 12bit resolution, 1-40MSps, single-end and fully differential input buffer.

TI-L500 Voltage Regulator
Thesys-Intechna
0.60 µm
XC06
PT
GDSII
Schematic

TI-L500 is a micro-power low dropout linear voltage regulator with fixed 5 V output voltage and input voltage of up to 40 V. ESD protection provided.

ADC15b008kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XC018
XH018
MP
GDSII
Schematic

Sigma-Delta-ADC, 15bit, 8-192kS/s sampling rate, up to 4 differential inputs

ADC15b008kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XC018
XH018
MP
GDSII
Schematic

Sigma-Delta-ADC, 15bit, 8-192kS/s sampling rate, up to 4 differential inputs

aopac02 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac02 is an internal frequency-compensated CMOS operational amplifier with p-mos input stage

aopac03 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac03 is a fast internal frequency-compensated CMOS operational amplifier with p-mos input stage

aopac05 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac05 is a low power internal frequency-compensated CMOS operational amplifier with nmos input stage

aopac06 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac06 is an internal frequency-compensated CMOS operational amplifier with n-mos input stage

aopac07 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac07 is a fast internal frequency-compensated CMOS operational amplifier with n-mos input stage.

aopac09 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac09 is an internal frequency-compensated CMOS operational amplifier with p-mos input stage and rail-to-rail output stage.

aopac10 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac10 is an internal frequency-compensated CMOS operational amplifier with rail-to-rail input stage and rail-to-rail output stage.

acmpc01 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc01 is a low-power two-stage CMOS comparator with n-mos input stage and a CMOS-output stage.

acmpc03 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc03 is a low-power two-stage CMOS comparator with n-mos input stage and a CMOS-output stage.

acmpc04 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc04 is a two-stage CMOS comparator with p-mos input stage and a CMOS-output stage.

acmpc06 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc06 is a two-stage CMOS comparator with p-mos input stage and a CMOS-output stage.

acmpc10 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc10 is a CMOS comparator with rail-to-rail input stage and rail-to-rail output stage.

acmpc11 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc11 is low offset CMOS comparator with rail-to-rail input stage and rail-to-rail output stage.

abgpc01 Bandgaps
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abgpc01 is a Brokaw, general-purpose bandgap reference source with high resistive poly resistor. 

abgpc03 Bandgaps
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abgpc03 is a badgap reference with high resistive poly resistor.

abiac01 Bias
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abiac01 is a bias voltage source (VBP1, VBN1) which needs a bandgap cell for biasing.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 121 to 150 out of 366

*Disclaimer:
The Intellectual Partner Network is a web database provided by X-FAB in cooperation with selected partners. Both X-FAB and a variety of different IP supplier offer their IP to customers using X-FAB’s foundry process. X-FAB will support customers to get in direct contact with the relevant IP supplier.

X-FAB will take no responsibility nor any liability whatsoever for the information or products offered or provided by the other IP suppliers at the database of the Intellectual Partner Network. X-FAB shall have no liability towards the customers for any use of and/or reliance of the products provided by the other IP suppliers at the database of the Intellectual Partner Network.

X-FAB's own IP is subject to a license agreement. X-FAB IP marked with “*” are part of the Master Kit or Master Kit Plus library. If you can not find the IP you are looking for, please contact the respective sales manager in your region. We continuously extend our libraries and offer a custom cell development service as well.