The 110 nm BCD-on-SOI technology platform (XT011) is the latest evolution of X-FAB's foundry offering, continuing the tradition of best-in-class offer for high-voltage automotive, industrial and medical applications.
The core platform leverages a competitive portfolio of digital libraries and non-volatile memory IP to be released throughout 2024, which, coupled with X-FAB’s high standards of design support, will enable first-time right success for your next-generation products.
In this webinar, X-FAB will present a first overview of the technology, available design solutions, support and release schedule, providing an initial introduction to the enhanced capabilities and benefits of this offer for their product roadmap.

Presenters:

Nando Basile, Technical Marketing Manager e-NVM
Lars Bergmann, Director Design Support
Zhenkun Chen, Program Leader XT011

Full physical 3D TCAD are often limited to smaller geometries. As the simulation domain increases in size an emulation approach is often taken with lower accuracy [1]. The 375V partial SOI LDNMOS is a large device with a complex, high aspect ratio, multi-region deep trench isolation (DTI) termination structure combined with the HW diode. Additionally, the device has a multitude of small floating silicon regions and a significant amount of silicon/oxide interfaces, coupled with floating field plates. As such, a complete 3D simulation was impossible. A new methodology of domain decomposition using Silvaco’s Victory 3D TCAD [3] has been introduced. The device is broken down into several elements, small enough to enable usage of Monte Carlo Implantation and physical annealing models. After the process simulation, the elements are then joined and re-meshed for device simulation.

Abstract—This paper presents the Radio Frequency (RF) circuit design and characterization of a Single Pole Double Throw (SPDT) switch. The switch is realized in a Gallium Nitride (GaN)/RF-SOI heterogeneous technology using “Micro-transferprinting”. The measured insertion loss and isolation are respectively below 0.65 dB and -12.7 dB up to 6 GHz. The large signal characterization using a continuous wave shows a hard breakdown at 36 dBm. On the other hand, the pulsed large signal measurement shows a 1dB input compression point of 48 dBm which meets the targeted value. This result confirms that the hard breakdown in CW is due to heat accumulation in the GaN. To address this issue, a heat evacuation technique for future hardware iteration is proposed. This heat evacuation technique should allow to achieve a CP1 of 48 dBm. And so, fully benefit from the advantages from both GaN and RF-SOI technologies on the same chip. 

Keywords—GaN, RF-SOI, Heterogeneous technology, Switch.

Silicon-based microfluidic systems

✓ Micro-manufactured fluidic structures for chip-scale handling and analysis of small quantities of fluids (liquids & gases)
✓ With noble metal electrodes integrated on silicon ASICs, as electro-chemical transducer interface, ready to be biofunctionalized for customized applications
✓ Using silicon technology: high integration density, stable and reproducible manufacturing process

Abstract
This paper provides a concise overview of X-FAB and the power electronics markets, with a specific focus on the wide bandgap semiconductors Silicon Carbide (SiC) and Gallium Nitride (GaN). The potential advantages of using power electronics for achieving carbon neutrality will also be discussed. Additionally, the challenges associated with integrating SiC and GaN into a CMOS manufacturing process will be presented. Finally, the paper concludes by offering an outlook on X-FAB's technology strategy for power electronics.

Abstract —Lateral Schottky barrier diodes were implemented in a thin body RF-SOI platform with CoSi2.  Both n-type and p-type device constructions were explored with various geometries and configurations.  Devices were modeled with TCAD, characterized, and their respective performance assessed.  In a demonstration in the targeted application as a zero bias detector, results of output voltage sensitivity to RF input power levels between –20 to 0dBm at frequencies up to 30 GHz are supportive to achieving mmW integrated circuits. 

Keywords — Schottky barrier diode, integrated, RF-SOI, zero bias detector, mmW

Abstract—This paper, presents a physically-based matching model that includes mismatch fluctuations in HiSIM_HV MOSFET model. Analytical expressions of the variation associated to the threshold voltage, current factor, and drift region resistor were developed and added to the compact model. The proposed model predicts accurately the mismatch in the drain current over a wide operating range and uses only three model parameters. This was validated through Monte Carlo simulations compared to experimental measurements on several device classes from X-FAB 0.18 um processes. The results of the drain current mismatch, the standard deviation of threshold voltage, and the standard deviation of the current factor are presented here and show good agreement between measurements and simulations.

Abstract—Timing jitter is one of the most important characteristics of single-photon avalanche diodes (SPADs), especially in applications requiring accurate photon timing, such as timecorrelated single photon counting (TCSPC) or LiDAR. In this article, we describe a measurement setup for the characterization of the timing jitter of actively-quenched SPADs using the TCSPC technique with a picosecond laser. By also describing the typical mistakes and potential pitfalls with such a setup, we aim to give a useful guideline on reproducing a setup with well-defined measurement uncertainty, in order to achieve comparable results
between devices of different manufacturers, both academic and commercial. In addition, we describe the physical cause of the jitter in SPADs to aid designers in the design of a new generation of low-jitter SPAD devices.

Abstract— The hafnium oxide based FeFET has attracted much attention due to its good scalability, high operating speed, and low power consumption. However, the integration of this device into CMOS technologies faces several challenges. Recently, the 1T1C FeFET concept with one transistor (1T) and a separate ferroelectric capacitor (1C) in the BEoL has been introduced. This new approach can be integrated into standard process technologies without significant changes at the transistor level. Herein, various stacks and integration schemes are investigated to optimize the BEoL MFM module. The impact of these stacks on key performance parameters of the BEoL MFM module, the 1T1C single-bit memory cell, and an 8 kbit test array is discussed.

(Webinar is presented in Mandarin)

More complex designs, shorter time to market and less time for engineering – these are the challenges IC designers are facing today. X-FAB will be addressing these topics to assist you in your design process and to support you to achieve First-Time-Right designs.

The shrinkage of critical lithographic feature size keeps introducing new challenges to the standard rule-based etch bias retargeting of Optical Proximity Corrections (OPC). This motivates the use of model-based instead of conventional rule-based etch bias retargeting. On the other hand, model-based retargeting comes with a substantial increase in run-time and complexity. 

X-FAB has been providing photodiodes for more than 20 years. In this webinar we are proud to introduce our new core process optimized for photodiodes. This has been developed based on the feedback and requests from you - our customers. The technology comes with a number of photodiodes with outstanding performance for UV, ambient and near-infrared light. It also offers a range of other devices to enable fully integrated low-noise sensor designs.

Be aware of the avalanche! Are you planning to integrate Avalanche Photodiodes (APD) or Single Photon Avalanche Diodes (SPAD) into your next IC design? If yes, you should watch this webinar replay. It will cover X-FAB's new APD/SPAD devices which come with a high photon detection probability of up to 18% for 850 nm wavelength and a low dark count rate. You will also learn about the integrated trigger diode which allows precise, real-time on-chip breakdown voltage detection without an external light source.

Whether you want to get a general overview of X-FAB’s large NVM portfolio, or already know the specific functionality, operating conditions and reliability requirements for your project, X-FAB provides an exhaustive and straightforward way to access relevant information.

This short video introduces the available tools for the quick access to helpful information about X-FAB’s NVM portfolio.

At X-FAB, we put great emphasis on reliability: all our technology platforms must comply with the tough requirements of the automotive industry, and our embedded NVM are no exception to that.

The whole test process for embedded NVM IP, from Design for Test (DFT) to qualification and production screening must be designed upfront and carefully executed to fulfill the automotive quality requirements.

This presentation provides a first overview and some key examples about the challenges and specific approaches in ensuring best-in-class quality for every single NVM IP from X-FAB and how customers can benefit from it.

Integration concept of GaN on SOI has been validated

Vertical coupling decreased thanks to the buried oxide

To our knowledge, this is the first time that this heterogeneous integration technique is used for RF applications
 

Is it worth to talk about the device characterization of breakdown voltage?
It should be a simple number extracted from a IV -curve
CMOS foundry point of view but there is more behind them

Most important parameter to monitor the CMOS process
Shift in the breakdown voltage refer to issues in the process
Therefore, the methodology how to extract the breakdown voltage or even the IV-curve is essential

By choosing the “AVLA” process module in XH018
Enable the primitive device of avalanche photodiode and single photon avalanche diode
Necessity to monitor the process for both devices
 

µTP is a novel technology for 3D and heterogenous integration.

Mass transfer and high placement accuracy are supported.

Devices/ ASICs of minimal dimensions can be integrated.

Various applications can benefit from the integration approach.

X-FAB‘s micro-transfer-printing activities were funded within several European and German projects realized by
ECSEL Joint Undertaking and the BMBF.

Abstract—This work reports on the progress of the heterointegration of GaN-HEMTs on CMOS wafers by micro-transferprinting (µTP). 200 V and 600 V class device types are successfully transferred from a GaN-on-Si source wafer to a processed CMOS target wafer. Technologies and process steps of the micro-transferprinting are briefly discussed. Both device types are characterized, before micro-transfer-printing on the original Si substrate, and after micro-transfer-printing on the CMOS wafer. The comparison discloses the impact of the micro-transfer-print process on the electrical performance.

The heterogeneous integration of RF-SOI and GaN shows high potential. Low power consumption / low noise / high linearity / small area.
High-linearity LNA demonstrator based on an heterogeneous amplifying cell was presented.

5G/6G requires innovative device technology platforms
 More bandwidth – mmW frequencies
 Higher data rates - linearity to support higher order modulation schemes
 Energy efficiency


GaN offers many attractive characteristics for RF/mmW
 III-V’s offer spec leadership in Ft, Fmax, etc
 However known weakness are low level of integration and cost


Heterogeneous integration of GaN on RF-SOI is pursued by X-FAB in Nano2022
 Transistor level vs functional block level integration
 High performance device integrated on a highly capable Si platform

Abstract: Several approaches for close integration of GaN power switches with silicon based CMOS logic are subject of technical evaluations and academic discussions. There is a common motivation for the different integration approaches to position gate driver logic and the power gate as close as possible to reduce parasitics and enhance efficiency. While academic research is and has to be done in all fields further industrial development can only occur within commercially promising areas. Therefore commercial boundary conditions impose economic limits to the usability of the different integration approaches to certain potential approaches. Basic cost estimation models for costs per wafer and costs per chip for different integration approaches are checked with real application driven IC examples.

Electronic design depends critically on the quality of the PDK - PDK verification becomes more and more important. 


With each semiconductor generation more functionality is integrated 

PDK verification increases the chance of first time right

 

Easily adopted for all XFAB technologies.
 

X-FAB offers for his foundry portfolio Avalanche Photodiodes and Single Photon Avalanche Diode devices for various application
Especially in the field of fluorescence detection a close collaboration with IMMS exists

The integration of the devices will be supported with different possibilities

Abstract—We present in this study a novel way to determine the three-dimensional (3D) temperature field of a Radio Frequency Silicon On Insulator (RF SOI) electronic chip, using several resistance temperature detectors (RTDs) embedded at different locations of the chip. The RTDs are designed and placed at different locations to experimentally obtain the temperature at key locations of the chip enabling the calibration of a multiphysical numerical model that provides the 3D temperature field in the whole chip under operating conditions. The obtained results provide useful insights on the role of different parameters (e.g. used materials properties, heat source power, substrate, boundary conditions, etc.) to engineers interested in the modelling and optimization of heat transport and thermal management of electronic chips for RF applications.

Calculation of effective lifetimes based on mission profiles is necessary. Very complex and a lot of manual work necessary with lifetime data from reliability specification.
Reliability Explorer “RelXplorer”
• models from reliability specification are the basis
• models include same safety margin as specification
• considers degradation mechanisms simultaneously
• calculates effective lifetimes based on Mission Profiles

The pace of development and industrialization of LOC devices has been growing – and will further accelerate. Smart integrated microfluidic systems are a key tool to tackle the future opportunities and challenges of digital healthcare. The COVID-19 pandemic being an enormous catalyst to disseminate digital healthcare. Serving a diversified portfolio and a strong customer base ensure steady growth. Technology standardization is the basis for a scalable business model.


Let´s transform the up coming challenges into opportunities together.

Abstract -- HV integrated lateral IGBTs are investigated as an attractive alternative to MOSFETs in integrated high-voltage (up to 230 V), low-power (5 - 500 mW) converters. A performance comparison of SJ-LIGBTs and SJ-MOSFETs is applied to define the design constraints and, consequently, to implement an optimized one-step power conversion topology with both device types. Measurement results of the topology with SJ-LIGBT show an up to 4.2 % higher efficiency in comparison to the SJ-MOSFET converter at 20.4 % smaller power-switch size.

For an IC to function reliably in the long-term, you need to be able to predict how a circuit is going to perform after a significant time in operation. Complementing silicon qualification, aging simulations come in handy to estimate the behavior in advance, to fulfill ISO 26262 requirements with regards to functional safety but also to help debug issues identified after reliability stress.
In this webinar, you will learn about the basics of reliability physics and the typical mechanisms that are responsible for transistor aging. The main influencing factors for device degradation will be described and options for limiting them will be discussed.
The presentation will also cover the flow for performing aging simulations in the Cadence design environment, providing examples that illustrate aging impact on circuits and how aging simulation can be used to uncover it.
In addition, the possibilities and limitations of aging simulation are highlighted and suggestions of usage in the day-to-day work of circuit designers are provided along with an overview of current aging model availability in X-FAB’s 180 nm processes and an outlook on upcoming models.

Modern medical applications rely on semiconductor technologies to build reliable, accurate and innovative devices. If you want to find out what types of technologies X-FAB provides and for which type of devices they can be used, then watch this webinar session covering the following topics:

Presenter:
Christine Dufour, Program Manager Microfluidics
Alexander Zimmer, Principal Engineer Process Development
Dr. Ulrich Bretthauer, Marketing Manager Medical

While BCD-on-SOI was traditionally considered a niche technology, it has seen a steep rise in adoption in recent years from all major market segments. The higher SOI substrate cost is more than compensated by the many benefits that come with BCD-on-SOI technologies. X-FAB developed its first BCD-on-SOI technology more than 25 years ago and now offers the most extensive foundry BCD-on-SOI technology portfolio.
Our modular processes combine the benefits of dielectric isolation through buried oxide (BOX) and deep trench isolation (DTI) with a wide range of robust HV CMOS, bipolar and well-matched passive primitive devices. XT018 is our leading 180 nm BCD-on-SOI technology solution supporting automotive AEC-Q100 Grade 0 designs and also satisfying the more stringent automotive reliability requirements which become challenging to deal with in Bulk BCD processes.
Learn more about the benefits of dielectric isolation in BCD-on-SOI technologies like latch-up immunity, voltage scalable isolation and ESD-protection, ease of design for circuits with multiple voltage domains and simpler ways to handle AC-coupling effects.

Presenter:

Tilman Metzger, Technical Marketing Manager High Voltage
Dr. Alexander Hoelke, Senior Member Process Development
Guido Janssen, Principal Engineer Design Support

Abstract — In semiconductor manufacturing, surface defects on wafers must be classified accurately for better yield management. To manage the increasing chip demand in speed and scale, automatic defect classification (ADC) system has been introduced. Most existing ADC systems utilize machine learning-based algorithms that require manual feature extractions and manual intervention such as human-based classification for accuracy and consistency. These methods are labour-intensive, unreliable, and highly prone to human error. Therefore, by leveraging on deep learning technologies, this paper proposes DLADC - an ADC system using a deep convolutional neural network (CNN) architecture for detecting and classifying semiconductor wafer surface defects. The proposed system takes Scanning Electron Microscope (SEM) images as input and outputs the defect’s class and location. The proposed system also sub-classifies particle-type defects into various sizing groups. Identification of defect types that occurred on wafer surfaces allows for better defect root cause analysis, and the additional information of defect size further serves as an essential indication of the origin of machine failure. The proposed DLADC promotes 2x time saving while achieving an improved accuracy of 93.69% based on experimental results with a real semiconductor defect dataset. Not only does DLADC outperforms the 70% classification performance of trained operators, but it also surpasses the 90% classification performance of industrially pragmatic defect classification.

Making chips for automotive has been X-FAB’s core business for about 30 years. With our technologies and IP, we support the transition from combustion engines to electrical vehicles. We make cars more efficient, comfortable and safer. 

This webinar series on X-FAB’s foundry solutions for automotive applications is held in Mandarin language. 

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2022年，整个汽车产业正经历着一个特殊时期：传统油车正逐步向电动化和智能化转变，同时，又遭受着全球疫情的影响和汽车芯片持续短缺的冲击。

X-FAB是一家国际化企业，在德国、法国、马来西亚和美国拥有6个生产基地。它致力于成为模拟世界的代工首选。

而近30年来，X-FAB始终致力于为汽车提供芯片。我们凭借技术和知识产权，能够支持从燃油汽车向电动汽车的转变。我们使汽车更高效、更舒适，更安全，使交通互联成为可能。

参加我们本场汽车主题研讨会，您将会全面了解X-FAB的汽车相关工艺。

Presenter:

Heming Wei, China Marketing Manager, X-FAB Group

The thinning of GaN wafers is especially delicate as the stabilizing Silicon is removed from already fragile wafers while applying mechanical stress. Two wafers broke not immediately during grinding but while handling afterwards. Currently, a backside process with thicker GaN wafers is being explored additionally. 

The advent of the Internet-of-Things brings new challenges in circuit design. The presence of circuits and sensors in harsh environments brought the need for methodologies that account for them. Since the beginning of the transistors, the temperature is known for having a significant impact on performance, and even though very low temperature sensitivity circuits have been proposed, no general methodology for designing them exists. This paper proposes an extension of the methodology presented in [15], generalizing the gm/ID technique for designing temperature-aware circuits that can
be used either on measurement data, analytically, or based on simulation models. This model is validated using measurements up to 250°C of X-FAB XT018 transistors and later with a Voltage-Controlled Oscillator circuit design example.

The modular TSV integration in thick wafers forms a complex system. This has to be considered in the process integration which might require small process or design changes in the front side process to enable the TSV integration.
To achieve a good Cu plating result in the 3-dimensional TSV structures the technical and chemical conditions have to be fulfilled (e.g., an optimized electrolyte has to be used). An optimization of the process parameters is needed, to achieve a stable process and minimal TSV resistance. This was successfully demonstrated.

In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.

Evolution of the technology landscape: Innovations required in Tx/Rx pathways with focus on realizing better amplifiers; Filtering transitions from acoustics; Potentially even faster switching times required to realize 5G-NR sub-frame spacing than current RF-SOI capabilities

A partial silicon on insulator (PSOI) is a widely recognized technology suitable for high-voltage (HV) architectures for power integrated circuits (PICs). Despite the added process complexity compared with SOI reduced surface field (RESURF), this technology offers a wider range of voltage ratings due to the action of the depletion layer in the handle wafer (HW), reduced parasitic capacitances
due to the extra volume of the depletion region in the HW, and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-D designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of HV integrated circuits (HVICs) where low ON-state resistance and reduced self-heating are essential requirements. This work presents
a PSOI technology platformwith the voltage ratings ranging from 45 to 400 V while providing low ON-state resistance, good hot carrier injection stability, as well as electrostatic discharge (ESD) capability of the HV devices. For example, for a 375-V rated laterally diffused MOSFET (LDMOSFET), this technology achieves an ON-state resistance of 1435mmm2, an over 50% improvement comparedwith the
state-of-the-artSOI technologies whilemaintaining competitive reliability.

Hafnium oxide based ferroelectric memory concepts like the FeFET will become increasingly important. They are good scalable, provide high operation speed, and consume low power. Just recently, an 1T1C FeFET concept with one transistor (1T) and one separated ferroelectric capacitor (1C) was demonstrated. This alternative approach is expected to overcome the drawbacks usually observed for the classic 1T concept like limited endurance, reduced retention, and high device-to-device variability. Electrically, the 1T1C FeFET consists of a series connection of the ferroelectric capacitor and the gate oxide capacitance. To operate at low voltages, a large fraction of the applied voltage must drop across the ferroelectric, which can be archived by optimizing the capacitance ratio. Herein, 1T1C
FeFETs with various capacitance ratios are fabricated and its impact on the electrical performance is discussed. Furthermore, the observed endurance of up to 108 field cycles illustrates the
great potential of the new concept.

A novel, low voltage LDMOS with a best in class specific on resistance 0.84mOhm.mm 2 has been achieved for a 12V breakdown. This excellent performance was enabled through a combination of conventional and unconventional architectural features implemented on a 110nm BCD on SOI technology.

The effect of Fluorine implantation after gate poly deposition and ex-situ Nitrogen anneal after thin gate oxide formation on Time-Dependent Dielectric Breakdown (TDDB) and Negative-Bias Temperature Instability (NBTI) improvement were studied in 0.13um Dual Gate Oxide CMOS Technology for 5V CMOSFETs. The TDDB lifetime was increased by about 1 order for 5V n/p-MOSFET by Fluorine implantation. The 5V p-MOSFET NBTI lifetime is increased an order of magnitude by Fluorine implantation and the ex-situ Nitrogen anneal. A reduction in the Flicker noise and interface trap density was observed for the group with Fluorine implantation and Ex-situ Nitrogen anneal followed by Fluorine implantation. This result demonstrates that optimization of Fluorine and Nitrogen within the gate oxide is necessary for reliability improvement of 5V CMOSFETs in 0.13um technology.

Rapid Thermal Processing (RTP) → key process in microelectronics
Use of large temperature range & varying processing times; Control of tool stability for high quality results; Tool Monitoring.

Temperature dependent monitoring by change of sheet resistance (Rs); Different wafer preparation for different temperature ranges; Repeatability and long-term stability investigations

This paper presents a novel 3D EM multi-technology simulation flow applied to the Micro-Transfer Printing (MTP) heterogeneous integration technique between GaN and RF-SOI. A modular approach is proposed which relies on the two technology PDKs, the definition of a Cu-RDL technology and an assembly library. This flow addresses the intricate nature of the conformal RDL between the two technologies. Additionally, it offers a complete traceability, physical verification as well as EM simulation environment. The flow is verified with two MTP demonstrators, a CPW transmission line and a DC-6GHz SPDT switch. A good hardware/model correlation is observed which validate the proposed flow.

Over the past years the semiconductor ecosystem has experienced an ever-increasing demand in wafer level integration and packaging technologies, driven by increased requirements on functionality, performance and efficiency. To support the increasing demand for advanced packaging capabilities X-FAB is offering 3D integration and wafer-level packaging methods to enable solutions for advanced system including analog mixed-signal ASICs, sensors, and MEMS. One particular technology out of this variety is the so called “micro-transfer-printing” (μTP) which enables an integration of small-scale devices – also referred to as chiplets – taken from a source and placed on a target wafer in a massively parallel way by applying an elastomeric stamp. Due to its numerous benefits for instance high throughput, integration of small and thin devices, high placement accuracy and short metallization tracks, μTP is regarded as an auspicious technology to support various System in Package (SiP) solutions. To offer this versatile technology, X-FAB has set-up a μTP pilot line for the development and industrialization of related processes in the MEMS clean room facilities in Erfurt, Germany. One focus of X-FAB is the development of print-ready SOI based CMOS ASICs. Print-ready refers thereby to a state in which the ASIC has been separated from the handle wafer and is solely carried by tether, a mechanical structure that keeps the device in place. The general process flow to make devices “print-ready” involves therefore, the chiplet singulation, the tether formation and the release etch.

Vertical interconnect access (Via) is an electrical structure designed as a bridge between multi-layers metallization of microelectronic silicon wafer. As a conductive gateway between metal layers, via structure is designated at all possible locations in a device base on integrated circuit (IC) routing requirement. As an effective current passageway, it is very common to have via structure fabricated underneath aluminum bonding pad. In the subsequent process of IC packaging, bond pad will be subjected to thermosonic wire bonding by using gold or copper wire. Certain devices will be subjected to ultrasonic wedge bonding of aluminum wire based on specific application.

In this work, a comprehensive study of the OPC test patterns is carried out for cross-sections of a substrate active layer for a 110nm node Shallow Trench Isolation (STI)/ Deep Trench Isolation (DTI) technology. We aim at a more reliable understanding of 3D profile effects on the active top of the silicon substrate. Coupled with the standard metrology data, our protocol would lead to a more accurate OPC etch bias rule-based retargeting. 

In this webinar, we will provide information about the key parameters of the photodiodes, the options available and how to use them for your design. The presenter will also share some tips and tricks for highly-sensitive photodiode arrangement using the newly integrated array wiring feature.

The webinar provides guidance on how to best use the APD/SPAD in order to achieve first-time-right designs by showcasing supporting tools like specific design libraries, evaluation chips for your own measurements, device models and a demonstrator from a partner institute.