273 entries
Published: Nov 2011

The power semiconductor industry has grown steadily in past two decades from $2.7 billion in 1992 and is expected to reach $13.1 billion in annual sales volume this year due to rapid proliferation of power electronics in many fields like telecommunication, automotive, new renewable energy system and energy conversion application. Among power transistor products, sales of modules built with Insulated Gate Bipolar Transistor (IGBT) are expected to increase 10 percent to $2.5 billion this year.
This paper gives an overview to different types of IGBTs available in current market as well as those under development.


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Published: Jan 2018

Negative Bias Temperature Instability (NBTI) had become one of the most significant device reliability subject reported in this day and age. Not only does NBTI impose a big impact on circuit functionalities as well as product lifetimes, but also becoming the prominent limiting factor for further CMOS technology scaling. Hence accurate characterization and thorough understanding of NBTI is essential to follow or go beyond the Moore’s Law. Nonetheless the existence of NBTI recovery becomes a huge obstruction to this effort; whereby fast reduction in the degradation of the device parameter occurs after end of electrical stress. Moreover device characterization within the measurement stage further increases the NBTI recovery corresponding to the increase in delay.


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Published: Sep 2011

Using a trench isolated 650V quasi-vertical n-channel DMOS as a starting point several new 650V transistor types have been evaluated. Mainly by design measures a 650V depletion DMOS, a 650V PMOS and a 650V IGBT were created for a modular integration into the process flow.


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Published: Feb 2018

The technology evolution worsens the stress level of microelectronic applications. The shrinking, higher interconnect stacks, the diversity of functions, higher frequencies and power densities lead to higher stress and more interaction of effects. At package and assembly level the densification of internal interconnections, the combination of RF, digital, analog and power, new materials like lead free solder, more aggressive processes and 3D packages deliver new challenges for reliability performance. Requirements of harsh environment applications, the use of consumer products in cars or challenging mission profiles for automotive applications trigger new considerations about reliability determination and description, higher robustness and resilience. Presently the processes, design rules, reliability tests and specifications fit to standards which base on established degradation models and quality assurance processes. But the existing standards like electromigration and stress migration tests for interconnects do not cover all of the new requirements especially due to mechanical stress and stress related limits.


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Published: Sep 2011

This paper presents a simple but effective way to improve an NMOS transistor’s ESD robustness for use in I/O pads. Simulation and physical failure analysis has been performed to identify the source of the ESD failure. Process splits have been performed primarily at LDD (Lightly Doped Drain) implant and salicidation process based on data presented in this paper.


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Published: Feb 2018

The downscaling in VLSI systems and the use of new materials requires the development of new test structures and in the case of harsh environment conditions the change of the test conditions to higher applied currents and test temperatures. Furthermore the application in wider operating areas and more challenging mission profiles leads to a concept of highly robust metallization stacks in a metal stack system up to eight levels. These stacks can contain a thick top metallization track for high current or RF application. Looking on the metallization systems of liners and cap materials as well as the current carrying metal themselves the differences in the coefficient of thermal expansion (CTE) of the materials lead to intrinsic tension and can result in fatal delamination of the metallization.


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Published: Sep 2011

Diodes inherent in a CMOS process are light sensitive and could be exploited as photodetectors. To detect light the photo generated carriers need to be separated by the electrical field of an internal pn junction. They are either generated inside the depletion region or can get there by diffusion. The depth where these carriers are generated depends strongly on the wavelength. The generation profile, the pn junction depth and the diffusion length all impact the spectral sensitivity.


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Published: Sep 2011

A study on the effect of process fabrication for MIM capacitors analog matching performance was carried out, impacts from the MIM dielectrics, capacitor top and bottom metal materials, capacitor metal etch, wet cleaning, annealing process will be revealed by comparing the Pelgrom coefficients, i.e. the dependence of difference in capacitance of the matching pairs with respect to their corresponding square root of capacitor areas, the smaller the difference the better the matching.


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Published: Jul 2011

An enhancement-mode Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) device has been developed in 0.13μm technology platform. The single-transistor (1-T) SONOS device in NOR Flash memory array utilizes n-channel cells. The development of 1-T SONOS is not an easy feat due to many disturbs experienced by the cells during operation.


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Published: Jul 2011

In low leakage MOS device fabrication, careful pn junction design is critical to control overall device leakage, such as Band-To-Band Tunneling (BTBT) and Gate-Induced Drain Leakage (GIDL) that are always taken into consideration by device designers. Source/Drain implantation also play a very important role in suppressing silicon dislocation effect, which increases implanted species transient-enhanced diffusion (TED) and induces shallow-junction leakage.


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