273 entries
Published: Dec 2012

We present a method for producing monolithically integrated CMOS optical filters with different and customerspecific responses. The filters are constituted by a Fabry-Perot resonator formed by two Bragg mirrors separated by a patterned cavity. The filter response can be tuned by changing the geometric parameters of the patterning, and consequently the cavity effective refractive index. In this way, many different filters can be produced at once on a single chip, allowing multichanneling. The filter has been designed, produced, and characterized. The results for a chip with 24 filters are presented.


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Published: Oct 2012

This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18┬Ám PSOIHV process. The superjunction drift region helps in achieving uniform electric field distribution in both structres but also contributes to the on-state current in the LIGBT.


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Published: Oct 2017

Thermal cooling of solder bumps using Under Bump Metalization (UBM) with isotropic undercuts can result in an increase in stress concentration. The stress concentration on the passivation layers can result in cracking, especially when there are surface defects. Opportunities in reducing thermal stress depend on the type of passivation layer design as well as other factors. In Part I of this series of papers, the focus is on optimizing the thickness of the standard passivation design.


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Published: Oct 2012

By this article an introduction of a highly robust metal track layout especially suitable for high current and temperature applications will be introduced. Starting with the reliability limitations normally observed for wide metal tracks, conclusions regarding the requirements for robust layout techniques will be drawn.


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Published: Oct 2017

Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material.


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Published: Oct 2012

Hermetic sealing is important regarding functionality and reliability for MEMS components. Typically this sealing is done on the wafer level using wafer bonding which simultaneously also provides mechanical protective caps. However, inner pressure and hermeticity testing and monitoring a still a critical issue; therefore, in this paper a test structure adapted to a MEMS foundry process for inertial sensors is introduced.


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Published: Oct 2017

Integration of Back End Of Line (BEOL) CMOS technologies with Wafer Level Packaging (WLP) is challenging, as mismatch of Coefficient of Thermal Expansion (CTE) between materials can result in thermo-mechanical induced cracking. This is especially true during reflow cooling of wafers after the solder ball attach process. Factors that contribute towards cracking can be from both the BEOL as well the WLP process steps.


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Published: Oct 2012

State of the art polymer strippers were identified and successfully evaluated as interesting alternatives as CMOS-compatible wet activations for semiconductor wafer direct bonding processes, including both high and low temperature annealing for bond interface strengthening. The polymer strippers achieve both excellent surface cleaning and wafer bonding activation by hydrophilization and are therefore a very interesting alternative as semiconductor direct wafer bonding pre-treatment.


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Published: Oct 2012

In this paper, optimization and physical scaling of the SONOS ONO triple layer are extensively evaluated, with detailed characterization of the Flash cell behavior. Reliability tests have demonstrated high temperature endurance and long-term data retention. The results have shown that the reliability requirement is attainable even with down scaling of the vertical component of the oxynitride charge trapping layer, which makes it feasible to operate the cell at a lower programming voltage.


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Published: Nov 2017

Approaches for wafer level 3D integration of CMOS and MEMS sensors are described in this paper.


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