273 entries
Published: Apr 2013

In this paper a modified MEMS foundry process allowing the production of 3D inertial sensors, such as accelerometers, gyroscopes and combinations, is introduced. The new MEMS process is suitable for a wide range of applications that use 3D accelerometers or gyroscopes. One-axis and three-axis designs can be produced with the same process, and the fabrication of complex inertial measurement units, in particular, the assembly process, is simplified.


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Published: Sep 2017

The downscaling in ULSI systems, extended life time requirements, the use under harsh environment conditions and new materials influence the reliability of components in terms of stress related defects, corrosion and radiation more and more.Harsh environment requires reliability goals which can be reached by a more application related reliability specification, by new processes, materials or design approaches. Thermal, electrical and mechanical behavior simulation can facilitate the necessary development work by the determination of the main failure mechanisms, the interaction of mechanisms, the degradation behavior of new materials and design.


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Published: Sep 2017

A tunable optical prism MOEMS based on the deformation of a liquid droplet is presented. An aluminum-nitride membrane is tilted by a novel type of thermo-mechanical actuator. The actuatio nprinciple is based on a thermo-mechanical modulation of the intrinsic stress in aluminum-nitride beams. Based on an analytical model, the key parameters of the actuator are optimized.


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Published: May 2013

The filters are constituted by a Fabry-Perot resonator formed by two Bragg mirrors separated by a patterned cavity. The filter response can be tuned by changing the geometric parameters of the patterning, and consequently the cavity effective refractive index. In this way, many different filters can be produced at once on a single chip, allowing multichanneling. The filter has been designed, produced, and characterized. The results for a chip with 24 filters are presented.


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Published: May 2013

This paper presents versatile HV lateral JFET design method on 0.18μm SOI BCD technology to achieve variable Vth(pinch-off voltage) and Idsat, without DIBL effect over full operating Vds range and scalable breakdown voltage capability on both N-ch and P-ch JFET. The significant advantage of a HV JFET compared to depletion MOSFET is the lower area consumption in real circuit design which due to higher Idsat values at Vgs=0V.


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Published: Sep 2017

The advantages of silicon-on-insulator (SOI) technology are reduced parasitic device capacitance, improved performance as well as smaller build area. Despite the gains of SOI technology to manufacturers, new challenges arise in Physical Failure Analysis (PFA). The process of delayering polysilicon or active layer becomes impossible without harming the top silicon. This study discussed the challenges of the current fastest, reliable and reproducible method to delayer polysilicon and divulge active layer. Current delayering method using 49% Hydrofluoric (HF) concentration and SC1 solution is proven to be a faster way to reveal polysilicon layer for Bulk Commentary Metal-Oxide Semiconductor (Bulk CMOS).


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Published: Dec 2012

The fabrication of semiconductor devices, even in the area of customer oriented business, is one of the most complex production tasks in the world. A typical wafer production process consists of several hundred steps with numerous resources like equipments and operating staff. The optimal assignment of each resource at each time for a certain number of wafers is vital for a efficient production process. Several demands defined by the customers and facility management must be taken into consideration with the objective to find the best tradeoff between the different needs.


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Published: Sep 2017

Today’s emerging technologies like photovoltaics, smart grid and electromobility are operating at high voltages which are interesting to be sensed on-chip for further processing.


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Published: Dec 2012

This paper evaluates the technique used to improve the latching characteristics of the 200V n-type superjunction (SJ) LIGBT on partial SOI. The initial design latches at about 23V with forward voltage drop (VON) of 2V at 300A/cm2. The latest design shows increase of latch-up voltage close to 100V without significant expense of VON.


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Published: Sep 2017

Standard design passivation layers on thick (> 3000 nm) top metalization has a susceptibility for cracking due to thermal stress. A Finite Element Analysis (FEA) simulation was done to investigate three different stress conditions i.e. cool down after Chemical Vapor Deposition, the increase, and the decrease in temperature during temperature cycling. The highest stress was realized during the increase in temperature during temperature cycling.


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