273 entries
Published: Sep 2017

Standard design passivation layers on thick (> 3000 nm) top metalization has a susceptibility for cracking due to thermal stress. A Finite Element Analysis (FEA) simulation was done to investigate three different stress conditions i.e. cool down after Chemical Vapor Deposition, the increase, and the decrease in temperature during temperature cycling. The highest stress was realized during the increase in temperature during temperature cycling.


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Published: Sep 2017

The downscaling in ULSI systems, extended life time requirements, the use under harsh environment conditions and new materials influence the reliability of components in terms of stress related defects, corrosion and radiation more and more.Harsh environment requires reliability goals which can be reached by a more application related reliability specification, by new processes, materials or design approaches. Thermal, electrical and mechanical behavior simulation can facilitate the necessary development work by the determination of the main failure mechanisms, the interaction of mechanisms, the degradation behavior of new materials and design.


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Published: Sep 2017

The advantages of silicon-on-insulator (SOI) technology are reduced parasitic device capacitance, improved performance as well as smaller build area. Despite the gains of SOI technology to manufacturers, new challenges arise in Physical Failure Analysis (PFA). The process of delayering polysilicon or active layer becomes impossible without harming the top silicon. This study discussed the challenges of the current fastest, reliable and reproducible method to delayer polysilicon and divulge active layer. Current delayering method using 49% Hydrofluoric (HF) concentration and SC1 solution is proven to be a faster way to reveal polysilicon layer for Bulk Commentary Metal-Oxide Semiconductor (Bulk CMOS).


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Published: Sep 2017

Today’s emerging technologies like photovoltaics, smart grid and electromobility are operating at high voltages which are interesting to be sensed on-chip for further processing.


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Published: Aug 2017

LEDs for luminaires:

  • low cost and high efficiency
  • dynamic (spectral) lighting


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Published: Aug 2017

Photodiodes integrated in X-FAB’s modular process platforms:

  • Can be combined with dozens other technology modules
  • High running reliable processes with internal second source
  • Leading low noise transistors for signal conditioning


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Published: Aug 2017

Semiconductor passivation layer cracking is considered critical as it can lead to moisture ingress into the device circuits and cause corrosion. The issue is more acute for high aspect ratio thick top metallization where the stress intensity factor (SIF) is higher.


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Published: Aug 2017

In this two-part series of papers, the goal is to reduce thermal stress impact on thick metal passivation. In Part II (this paper), the relationship between passivation thickness and the thermal stress was established using Response Surface Methodology Design of Experiments (RSM DOe).


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Published: Aug 2017

Standard design passivation layers on thick (> 3000 nm) top metalization has a susceptibility for cracking due to thermal stress. In this two part series of papers, Finite Element Analysis (FEA) simulation with Comsol Multiphysics was used to understand the impact of thermal stress. In Part I (this paper), three different thermal stress conditions were investigated i.e. cool down after Chemical Vapor Deposition (CVD), the increase, and the decrease in temperature during temperature cycling.


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Published: Aug 2017

Bond pad quality and reliability evaluation is part of important structure test for wafer fabrication. In order to ensure production consistency, and part of continuous monitoring, as well as new process qualification, bond pad evaluation through wire bond is required. Usually the test was conducted by proceed through standard IC packaging such as wafer saw, die attach and wire bond to simulate actual mass production environment. Optionally this can also be done by using wafer level wire bond. Main advantage of wafer level wire bond is shorter test cycle as compare to conventional package level bonding. This could be a significant time saving especially in the fast pace semiconductor field. Key concern of wafer level bonding is the correlation of bonding performance as compare to real application in the field.


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