273 entries
Published: Jul 2013

XDH10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 220V net supply. The typical breakdown voltage of the HV DMOS devices is >350V or >650V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die.


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Published: May 2012

XDM10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 110V net supply. The typical breakdown voltage of the HV-DMOS devices is >350 V or >275V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die.


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Published: Jul 2017

Sensor interfacing is a crucial component for today’s systems in many application domains. Especially in automotive and manufacturing fields, high temperatures are encountered. For extracting the typically small sensor signals, an interface near the sensor is needed to provide a high-accuracy and robustness.


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Published: Jul 2017

In view of reducing the process development cycle times with plausible time-to-market goals, it is of great demands to speed up the assessment pace, but at the same time not to jeopardize for the high level of quality requirements. Highly robust designs and process margins are the key differentiators and should be enforced in particular for the automotive markets. In this work, development of the fast wafer-level reliability (FWLR) `pulsed' tests that are performed in a relatively short time span under highly accelerated stress conditions on the standard parametric test station (PCM) is revealed here. This is incredibly useful and saving a lot of time especially for compact DOE analysis.


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Published: Jun 2013

Lifetime determination is one of the reliability key tasks to have an accurate estimation of the period of time that can still survive with a certain confidence level under the specific operating conditions to perform the respective function of the applications. Various reliability tests have been designed to reveal and assess the respective wear-out degradation mechanisms.


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Published: Aug 2017

Bond pad quality and reliability evaluation is part of important structure test for wafer fabrication. In order to ensure production consistency, and part of continuous monitoring, as well as new process qualification, bond pad evaluation through wire bond is required. Usually the test was conducted by proceed through standard IC packaging such as wafer saw, die attach and wire bond to simulate actual mass production environment. Optionally this can also be done by using wafer level wire bond. Main advantage of wafer level wire bond is shorter test cycle as compare to conventional package level bonding. This could be a significant time saving especially in the fast pace semiconductor field. Key concern of wafer level bonding is the correlation of bonding performance as compare to real application in the field.


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Published: Aug 2017

Standard design passivation layers on thick (> 3000 nm) top metalization has a susceptibility for cracking due to thermal stress. In this two part series of papers, Finite Element Analysis (FEA) simulation with Comsol Multiphysics was used to understand the impact of thermal stress. In Part I (this paper), three different thermal stress conditions were investigated i.e. cool down after Chemical Vapor Deposition (CVD), the increase, and the decrease in temperature during temperature cycling.


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Published: Aug 2017

In this two-part series of papers, the goal is to reduce thermal stress impact on thick metal passivation. In Part II (this paper), the relationship between passivation thickness and the thermal stress was established using Response Surface Methodology Design of Experiments (RSM DOe).


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Published: Aug 2017

Semiconductor passivation layer cracking is considered critical as it can lead to moisture ingress into the device circuits and cause corrosion. The issue is more acute for high aspect ratio thick top metallization where the stress intensity factor (SIF) is higher.


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Published: May 2013

This paper demonstrates a novel lateral superjunction (SJ) lateral insulated gate bipolar transistor (LIGBT) fabricated in 0.18μm partial silicon on insulator (PSOI) HV process. The results presented are based on extensive experimental measurements and numerical simulations.


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