273 entries
Published: Nov 2017

I. What is Micro-Tranfer-Printing?
II. MICROPRINCE - Pilot Line for Micro-Transfer-Printing
III. Optimization of Tether Design and Release Etch


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Published: Nov 2017

I. Introduction
II. NVM Technology & Design
III. NVM Product Integration & Application


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Published: Nov 2017

The shift of the threshold voltage (Uth) in high voltage metal-oxide-semiconductor field effect transistors (n-MOSFET) with source and drain regions created by an As-implantation with different implanters was investigated. By analyzing the capacitance-voltage curves recorded in metal-oxide-semiconductor structures with different thicknesses of SiO2 and different shapes we found that the shift of Uth in the n-MOSFETs was correlated with the presence of implantation induced defects in the gate oxide. These defects were stable even after the heat treatments at about 1200 K and they appeared in SiO2 due to different pressures in the implantation chamber and different types of gas.


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Published: Nov 2017

Tomorrows integrated power electronic systems require more efficient power conversion solutions at lower costs.


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Published: Oct 2017

I. Introduction
II. Foundry service as part of the value chain
II.i. Process development
II.ii. Open platform processes


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Published: Oct 2017

Device characterization during development requires intensive measurement activities and over temperature measurement is a must for automotive application. Manual measurement is simply not efficient and time consuming for large data collection. Automation in measurement and report generation is needed to improve the efficiency during device characterization campaign.


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Published: Oct 2017

Integration of Back End Of Line (BEOL) CMOS technologies with Wafer Level Packaging (WLP) is challenging, as mismatch of Coefficient of Thermal Expansion (CTE) between materials can result in thermo-mechanical induced cracking. This is especially true during reflow cooling of wafers after the solder ball attach process. Factors that contribute towards cracking can be from both the BEOL as well the WLP process steps.


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Published: Oct 2017

Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material.


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Published: Oct 2017

Thermal cooling of solder bumps using Under Bump Metalization (UBM) with isotropic undercuts can result in an increase in stress concentration. The stress concentration on the passivation layers can result in cracking, especially when there are surface defects. Opportunities in reducing thermal stress depend on the type of passivation layer design as well as other factors. In Part I of this series of papers, the focus is on optimizing the thickness of the standard passivation design.


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Published: Sep 2017

A tunable optical prism MOEMS based on the deformation of a liquid droplet is presented. An aluminum-nitride membrane is tilted by a novel type of thermo-mechanical actuator. The actuatio nprinciple is based on a thermo-mechanical modulation of the intrinsic stress in aluminum-nitride beams. Based on an analytical model, the key parameters of the actuator are optimized.


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