273 entries
Published: Oct 2013

This webinar session provides guidance through the EDA environment and describes the interaction among EDA tools, design methodology and PDKs to optimize the design process. It uses selected reference flows and best practice examples for critical components during the design phase.


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Published: Oct 2013

The fabrication of semiconductor devices, even in the area of customer oriented business, is one of the most complex production tasks in the world. A typical wafer production process consists of several hundred steps with numerous resources including equipment and operating staff. Smaller foundries with a high product mix and a low technology volume need reasonable assignments of each limited resource at each time. Several requirements defined by the process requirements, customers and management must be taken into consideration with the objective to find the best trade-off between the different needs.


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Published: Oct 2013

Wafer Bonding is a key process step in microsystem technologies. By the stacking and joining of semiconductor wafers, three-dimensional structures can be created, which are not realizable with classical thin-film technologies based on layer deposition and etching steps. Wafer bonding can be used at the beginning of the wafer process to prepare special substrates with benefits in the subsequent technology processes.


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Published: Sep 2013

This webinar session focuses on the importance of proper characterization data for successful analog design, and discusses how modeling and process characterization can make life easier for analog design engineers. It covers statistic modeling approaches, model quality assurance and process calibration.


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Published: Sep 2013

Showing first-time-right performance statistics from X-FAB's customer base, this first session outlines the challenges involved in achieving first-time-right analog designs. It talks about what impact the choice of process architecture makes, and discusses the pros and cons of different process architectures including SOI and BCD.


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Published: Sep 2013

At the moment the miniaturisation of integrated circuits for consumer electronics means to decrease the size of Cu interconnects below 100 nm, while a lifetime of 3–5 years has to be guaranteed. For industrial and automotive applications wider Al interconnects (~350 nm) are used, but an extreme low rate of failures (0.1 ppm) has to be reached to produce reliable end-products including dozens of components. A further progress in the development of high-end electronics and more complex industrial products needs a better prediction of possible failure mechanism and the related time to failure of the chosen technology. This investigation is focused on migration induced void formation and combines the results of process simulations, for the back end of line, (intrinsic pre-stress) with the dynamic simulation of the migration induced material movement in the interconnects.


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Published: Sep 2013

Highly robust metallizations m ICs for high temperature and high current applications are needed. Special thick metal layers often known as "power metals" are added to achieve a higher current capability. But these metallizations suffer from reliability limitations as well.


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Published: Jul 2013

Robust metallizations for harsh environment and high current applications in integrated circuits are required for automotive or industrial applications. To achieve a higher current capability so called ‘‘power metals’’ are used. The new concept of slotted geometries shows a better robustness towards degradation due to electromigration.


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Published: Jul 2013

For most devices sitting on SOI wafer, there is a consideration of backside coupling effect. This phenomenon becomes catastrophic if the device sits on the SOI wafer is an IGBT which consists n-p-n-p structure and employs both the partial SOI and DTI technique. Earlier leakage had been found during development of 200V superjunction lateral IGBT (SJ LIGBT) on partial SOI.


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Published: Jul 2013

XDH10 is X-Fab´s dielectric trench insulated smart power technology. Main target applications are analog switch ICs, driver ICs for capacitive, inductive and resistive loads and EL / piezo driver ICs for applications using 220V net supply. The typical breakdown voltage of the HV DMOS devices is >350V or >650V. The modular process combines DMOS, bipolar and CMOS processing steps that are compatible with dielectric insulation to provide a wide variety of MOS and bipolar devices with different voltage levels within a dielectric bi-directional high voltage trench insulation on the same die.


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