273 entries
Published: May 2015

This paper presents a new SOI BCD technology at the 0.18μm node to fulfill the requirements for smart power IC technology targeted for automotive application. Built on a 1.8V and 5.0V CMOS core, there are 40V and 60V rated N/Pch MOS, with 25mΩ.mm2 RonA/57V BVdss having been achieved for the 40V NMOS with excellent process stability.


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Published: Apr 2015

For mixed signal applications it is necessary to have metallization which are able to carry high currents. Also the on chip integration leads to special requirements on the metallization concerning their robustness. A common method for the determination of interconnect lifetime is described in JP001A and based on Black's law and the measurement of time to failure, medium stress current density and medium stress temperature.


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Published: Mar 2015

An increasing number of applications such as automotive engine management require electronic systems which operate reliably at temperatures above 150°C. Designers are facing the challenges of dealing with changes in electrical characteristics, higher leakage current and thermally accelerated degradation.This webinar looks at the device physics, electrical properties of MOSFETs and NVMs, and degradation mechanisms at elevated temperatures up to 200°C. It will discuss the behaviour of CMOS when it is operated at higher temperatures and how the issues which arise can be mitigated by process architecture and design techniques. In addition, X-FAB’s broad portfolio of bulk and SOI CMOS processes for use at high temperatures up to 225°C will be presented.


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Published: Mar 2015

The design of a system containing integrated MEMS is still a task which requires deep knowledge of the MEMS process itself. Even with the availability of COT MEMS foundry processes, which support the design of MEMS according to process-specific design rules, the quality of results heavily depends on the skills and know-how of the involved designers. Reasons for this are the lack of a sufficient design automation, which would implement and verify parts of the expert knowledge, as well as the missing process abstraction, which would encapsulate the foundry-specific rules and parameters.


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Published: Mar 2015

The highly robust metallization offers with higher temperature and current density, a higher electromigration stability and better thermo-mechanical robustness in applications. For Emerging Applications a highly robust metal stack was developed. The difficulty of a robust metallization consists in the complex form of the metal tracks.


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Published: Mar 2015

For gate driver ICs in three phase power applications level shifters with more than 900V operating voltage are required. The extension of the voltage rating of an existing trench isolated SOI process was done with different device concepts: Serial stacking of lower voltage devices was evaluated as an alternative approach to conventional quasi-vertical and charge compensated lateral devices which need layout and material modifications. 


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Published: Dec 2014

A vertically stacked quad junction photo detector (PD) with an enhanced spectral responsivity for blue light is presented. This PD is implemented in a 0.35 μm high voltage CMOS technology.


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Published: Oct 2014

Design for reliability nowadays is of great importance on guaranteeing the first time right process applications with robust enough margins, and thus it becomes more and more popular integrated to the design flow considerations. Common failure mechanism: plasma charge damage (PCD), due to its occasional nature of the dielectric breakdown, it is usually not easy to be validated from simulations or even justified by enough silicon data. Besides, in order to achieve a fast assessment of reliability aspects, tests done at wafer level would be most preferable to be used with great improvement in response time, and without jeopardize the accuracy of the analysis and justifications. In this work, we will describe the methodology used and provide examples of determining the design window on one of the major primitive devices: metal-insulator-metal capacitors by means of the designs’ limitation evaluation from reliability assessments.


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Published: Sep 2014

For a robust metallization design it is necessary to know, how strong the influence of the tungsten via alignment affects the physical behavior. Is there an optimal overlap existing ? Have the alignments have a noticeable effect on the reliability and performance of test structures ? For the upstream line no influence of the misalignment on the lifetime was found. Why?


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Published: Sep 2014

The miniaturization process of CMOS components creates new challenges for the development of integrated circuits. Especially the connections with a tungsten via between two metal layers can be a problem. Changes in geometry can bear on reliability problems. For a robust metallization design it is necessary to know, how strong the influence of the tungsten via alignment affects the physical behavior. 


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