284 entries
Published: Dec 2019

In this work we demonstrate application of Al/Ge eutectic vacuum packaging of a CMOS/MEMS wafer to a Cap wafer for infrared sensors. Optimum Al/Ge integration and bonding procedure result into noticeable enhancement of thermopile-pixel responsivity. In addition, critical parameters along process variation, which can be beneficial to other types of CMOS/MEMS devices with variable process integration approaches, are discussed. 


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Published: Oct 2019

Abstract This contribution investigates the suitability of chip-level tests for the mechanical characterization of thin films in a mass production environment. The parameters of intrest are the Young´s modulus, the residual mechanical stress as well as its gradient along the film thickness and the critical fracture stress. For the measurement of these parameters the electrical measurement equipment for end of line testing in CMOS industries is used.


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Published: Oct 2019

X-FAB maintains an active ecosystem (X-Chain). X-Chain represents X-FAB’s most qualified and suitable service partners. Numerous actors have relevant experience serving the medical market 
X-FAB’s IP-Portal offers a variety of design IP from analog building blocks to digital cores.


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Published: Sep 2019

Polysilicon is an integral part of many devices in all CMOS process. Very consistent and accurate electrical performance of such material is a need of those devices used in Circuit Under Pad (CUP) applications. This paper presents an investigation on stress impact of probe insertions on two bond pad metal options i.e. METMID and METTHK on a polysilicon resistor placed under the bond pad. Probing results in residual stress on both Back End Of Line (BEOL) as well as Front End Of Line (FEOL) structures. This residual stress would impact the electrical properties of the polysilicon material used in such devices. In this study, such electrical impact is measured in terms of change in resistance of a polysilicon resistor which was placed underneath the bond pads.


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Published: Sep 2019

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Published: Aug 2019

Have you ever sat in front of your IC layout and asked yourself how you need to place guard rings to mitigate unwanted parasitic effects?
If you take the safe approach you may waste precious layout area which increases the overall footprint of your IC. Just imagine if you could know where peaks of substrate current are in order to effectively predict the parasitic effects for countermeasures. To address this challenge X-FAB has enabled PNAware XSUB – a substrate analysis tool developed by the Swiss EDA software vendor PN Solutions.

In this webinar, we will demonstrate the tool which is enabled by X-FAB's PDK environment using examples from the 180 nm high-voltage technology (XH018).


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Published: Jul 2019

Adhesive wafer bonding using laminated photosensitive dry-resist offers many advantages and can be used to realize advanced, CMOS integrated, volume manufacturable lab-on-a-chip devices. The relatively low bond temperatures involved allow the wafer-level hybrid integration of a range of substrates, e.g. CMOS wafers with structured MEMS glass wafers. The dry-film polymer acts as the adhesive interlayer and can also be lithographically patterned to form sealed microfluidic fluid channels and chambers after the bonding process.


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Published: Mar 2019

Harsh wafer level probing has a higher chance of causing inter metal dielectric (IMD) cracking compared to wire bonding. This work explores the stress induced by probing by utilizing dynamic Finite Element Analysis (FEA) structural mechanics simulation. A thicker bond pad (METTHK with thickness of 3000 nm) can reduce the IMD stress caused by harsh wafer level probing.


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