IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
XTAL5M Crystal Oscillators
Suter IC-Design AG
0.18 μm
XC018
MP
GDSII
Schematic

Low power crystal oscillator for resonator with fast start-up, available for XC018/XH018 MOS3LP, including pads, different pads on request.

VREG1_8 Voltage Regulator
Suter IC-Design AG
0.18 μm
XC018
MP
GDSII
Schematic

Low power voltage regulator for 1.8V logic, requires only an external capacitor, available for XC018/XH018 MOS3LP and MOS5LP, different option available on request.

Tunable Cryptography Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Symmetric Cryptography, Asymmetric Cryptography, Hash and MAC functions. Embedding the state-of-the-art countermeasure against high order side-channel attacks, Tunable Crypto IP allows you to reach the perfect balance between Security, Speed, and Area.

TRNG Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

True Random Number Generators are used to generate statistically independent sets of bits for various applications such as One Time Pad cryptography, key generation, seeds for PRNGs, masks to protect an implementation against side-channel analysis.

TI-RF-Switch Analogue Switches
Thesys-Intechna
0.35 μm
XH035
VS
GDSII
Schematic

The TI-RF-Switch is a broad-band dual SPDT analog switch containing two single-pole double-throw switches. Used CMOS technology provides high isolation and low insertion loss at frequencies up to 1 GHz.

TI-RF-MUX Multiplexer
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-MUX is a 4-to-1 RF multiplexer designed with an internal current feedback output amplifier whose gain can be adjusted externally. There is a possibility of optional usage of two 4-to-1 devices as one 8-to-1 multiplexer. ESD protection provided.

TI-RF-DRV Driver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-DRV is a fully differential RF driver for differential signal processing applications. Common-mode level of differential outputs is adjustable that allows to shift easily the input signals for driving single-supply ADCs. ESD protection provided.

TI-RF-CMP Comparators
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-CMP is a low power CMOS RF comparator with 4 ns propagation delay and latch function. ESD protection provided.

TI-Manchester Transceiver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-Manchester is a dual data bus transceiver designed for receiving CMOS/TTL Manchester II data, converting it and transmitting through a stepup transformer to the data bus...

TI-L500 Voltage Regulator
Thesys-Intechna
0.60 µm
XC06
PT
GDSII
Schematic

TI-L500 is a micro-power low dropout linear voltage regulator with fixed 5 V output voltage and input voltage of up to 40 V. ESD protection provided.

TI-16PI/150M ADC
Thesys-Intechna
0.18 μm
XT018
VS
GDSII
Schematic

TI-16PI/150M is a dual-channel fully differential 16-bit ADC with pipelined architecture optimized for high dynamic performance at sample rates up to 180 MSPS.

Securyzr Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure-IC Securyzr provides a complete range of security features while addressing all the state-of-the-art threats against embedded systems. Securyzr is customized according to each market's and client's specific requirements.

Secure Monitor Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure-IC Monitor gathers security events in real time and provides a high level interface to use security functions of the SoC. The Secure Monitor is a comprehensive toolbox, ideal for building a security policy and protecting sensitive assets.

Secure JTAG Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

The Joint Test Action Group (JTAG) is the IEEE1149.1 Standard Test Access Port (TAP) and Boundary-Scan Architecture. The TAP interface is a backdoor for hackers. Secure-IC offers a set of tools to secure the access to the device: Secure Test Access Port.

Secure Clock Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure Clock IP core is intended to clock feed all desired hardware, creating a secure clock domain within the System on Chip host. ...it also fuzzes the relevant fault injection moment used by fault injection attacks.

Secure Boot Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Provides a secure root-of-trust with a high level of resistance against malevolent attacks, ensures integrity of the SoC security features and guarantees that the firmware is genuine. Optionally, it ensures the firmware’s confidentiality

Scrambled Bus Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Scrambled Bus IP masks all data carried on the bus with random variables generated locally by cryptographic primitives. Features:
• On-the-fly masking and unmasking, no additional latency
• Transparent for bus masters and slaves
• etc.

 

 

RINGVCO1 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_VCO_CELLS. RINGVCO1 is a fully integrated VCO. It should be biased by the RF bias cell. It consists of a ringoscillator that is tuned by switching the delay chain between 2 and 4 delay stages. The transition between the two borders i

qrcoc09_1v8 Oscillator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V arcoc09_1v8 is a robust 40MHz RC oscillator with internal R and C. Frequency independent on load capacity.

PWM Other
Ridgetop Group
0.35 μm
XH035
ID
GDSII

250kHz PWM for DC-DC converters

PUF Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

PUF IP Core is a secret key generation system based on Physically Unclonable Functions (PUF). This feature allows a real protection against the reverse-engineering techniques compared to traditional methods that store the key in non-volatile memory.

PGA180nm AFE Amplifier
Fraunhofer IIS/EAS
0.18 μm
XC018
XH018
PT
Schematic
GDSII

Programmable Gain Amplifier, Gain settings 0.5 – 128 (9 steps), (optional) 8-to-1 input mux, (optional) internal chopper stabilizer, temp range from -40 to 175°C

PA Power Amplifiers
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_PA_CELLS. PA is a non-linear Power Amplifier that is intended for the transmission of ASK and FSK signals. Its output power level can be digitally controlled in 4 steps. It should be biased by the RF bias cell.

OEIC_Sensitive Optical Receiver Channel
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. OEIC_Sensitive is a sensitive DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.

OEIC_Fast Optical Receiver Channel
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. OEIC_Fast is a fast DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.

MR74039 Other
Moortec Semiconductor Ltd
0.35 μm
XH035
ID
GDSII
Verilog

The MR74039 is a fully integrated temperature sensor with a 12 Bit digital output designed in the XFab 0.35um XH035 process. It utilises a 12 bit Sigma Delta ADC for increased precision (0.25ºC). The temperature measurement range is fr

MIXER Mixer
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_MIXER_CELLS. MIXER is a down conversion mixer based on a Gilbert cell topology. It should be biased by the RF bias cell.

LNA3 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA3 is a low noise amplifier with on-chip inductor. It should be biased by the RF bias cell.

LNA2 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA2 is a low noise amplifier. It should be biased by the RF bias cell

LNA2 LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA2 is a narrowband low noise amplifier. It should be biased by the RF bias cell.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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The Intellectual Partner Network is a web database provided by X-FAB in cooperation with selected partners. Both X-FAB and a variety of different IP supplier offer their IP to customers using X-FAB’s foundry process. X-FAB will support customers to get in direct contact with the relevant IP supplier.

X-FAB will take no responsibility nor any liability whatsoever for the information or products offered or provided by the other IP suppliers at the database of the Intellectual Partner Network. X-FAB shall have no liability towards the customers for any use of and/or reliance of the products provided by the other IP suppliers at the database of the Intellectual Partner Network.

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