IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
ADC12b017kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XH018
PT
GDSII
Schematic

Cyclic single ADC, 12bit resolution, 17kSps, 0.5 LSB INL, 12bit ENOB, 50µW power consumption.

ADC12b054kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XH018
PT
GDSII
Schematic

Cyclic single ADC, 12bit resolution, 54kSps, 1.6 LSB INL, 10.5bit ENOB, 370µW power consumption

ADC16b013kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XH018
PT
GDSII
Schematic

Cyclic single ADC, 16bit resolution, 13kSps, 12.7 bit ENOB, 50µW power consumption

ADC12b020MS350nm ADC
Fraunhofer IIS/EAS
0.35 μm
XH035
PT
GDSII
Schematic

Pipelined ADC, 12bit resolution, 20MSps, 9.6 bit ENOB@2MSps, 9.2 bit ENOB@20MSps,  2 LSB INL, 125mW power consumption

ADC12b040MS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XC018
XH018
MP
GDSII
Schematic

Pipeline ADC, 12bit resolution, 1-40MSps, single-end and fully differential input buffer.

ADC15b008kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XC018
XH018
MP
GDSII
Schematic

Sigma-Delta-ADC, 15bit, 8-192kS/s sampling rate, up to 4 differential inputs

ADC15b008kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XC018
XH018
MP
GDSII
Schematic

Sigma-Delta-ADC, 15bit, 8-192kS/s sampling rate, up to 4 differential inputs

PGA180nm AFE Amplifier
Fraunhofer IIS/EAS
0.18 μm
XC018
XH018
PT
Schematic
GDSII

Programmable Gain Amplifier, Gain settings 0.5 – 128 (9 steps), (optional) 8-to-1 input mux, (optional) internal chopper stabilizer, temp range from -40 to 175°C

IPMS_430 Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

Compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features:
- 16 bit Risc CPU
- 7 address modes for source operands
- several low power features

IPMS_16CXX Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

8 Bit Microprocessor. The core IPMS_16CXX is a 8-bit microcontroller compatible to PIC 16CXX-family from Microchip.

IPMS_CAN_FD Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

IPMS_CAN is a CAN bus controller that performs serial communication according to the CAN 2.0B and the CAN FD specification.It is compatible to ISO CAN FD andthe non-ISO (Bosch) CAN FD standard and has extended time stamp and time trigger capabilities.

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol used in low cost automotive networks. It enables cost efficient bus communication for applications where the bandwidth of CAN is not required. Support of LIN specification 2.2A

IMMS SENT Transmitter Soft IP
IMMS GmbH
All Geometries
All Processes
PT
Verilog

Silicon-proven Verilog implementation of a flexible configurable SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. Up to 16-bit data from two independent sensors.

MR74039 Other
Moortec Semiconductor Ltd
0.35 μm
XH035
ID
GDSII
Verilog

The MR74039 is a fully integrated temperature sensor with a 12 Bit digital output designed in the XFab 0.35um XH035 process. It utilises a 12 bit Sigma Delta ADC for increased precision (0.25ºC). The temperature measurement range is fr

DAC-7bit-0.6u DAC
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS, output to pos rail

DC-DC Converter DC/DC Converters
Ridgetop Group
0.60 µm
XC06
ID
GDSII

Ultra high efficiency programmable output voltage over wide input voltage range, buck/boost. Input: 1.5V - 15V. Output 2V-6V

Comparator 0.6u Comparators
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Ultra Low Power, Wide Supply Range, CMOS

BGR 0.6u Bandgaps
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS

PWM Other
Ridgetop Group
0.35 μm
XH035
ID
GDSII

250kHz PWM for DC-DC converters

High V Input Cell Other
Ridgetop Group
0.35 μm
XH035
ID
GDSII

High Voltage Input for input voltages up to 100V

Active Shield Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Attacks against digital circuits can be performed by directly tampering with the device's internal structure. Active Shield technology is designed to deter such intrusive attacks by placing a mesh over the sensitive parts of the circuit and monitor

CyberCPU Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

CyberCPU comprises technologies for detecting cyber-attacks targeted to hijack and take the control of the CPU. CyberCPU technologies are available as portable security features to be integrated in a targeted CPU architecture or as a ready to use IP Core.

Digital Sensor Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Cryptography attack can inject one or several faults into a device disrupting its functional behavior. The Digital Sensor detect various threats belonging to the family of Fault Injection Attacks (FIA) : Input clock frequency, Input Voltage, Temperature,

PUF Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

PUF IP Core is a secret key generation system based on Physically Unclonable Functions (PUF). This feature allows a real protection against the reverse-engineering techniques compared to traditional methods that store the key in non-volatile memory.

Scrambled Bus Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Scrambled Bus IP masks all data carried on the bus with random variables generated locally by cryptographic primitives. Features:
• On-the-fly masking and unmasking, no additional latency
• Transparent for bus masters and slaves
• etc.

 

 

Secure Boot Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Provides a secure root-of-trust with a high level of resistance against malevolent attacks, ensures integrity of the SoC security features and guarantees that the firmware is genuine. Optionally, it ensures the firmware’s confidentiality

Secure Clock Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure Clock IP core is intended to clock feed all desired hardware, creating a secure clock domain within the System on Chip host. ...it also fuzzes the relevant fault injection moment used by fault injection attacks.

Secure JTAG Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

The Joint Test Action Group (JTAG) is the IEEE1149.1 Standard Test Access Port (TAP) and Boundary-Scan Architecture. The TAP interface is a backdoor for hackers. Secure-IC offers a set of tools to secure the access to the device: Secure Test Access Port.

Secure Monitor Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure-IC Monitor gathers security events in real time and provides a high level interface to use security functions of the SoC. The Secure Monitor is a comprehensive toolbox, ideal for building a security policy and protecting sensitive assets.

Securyzr Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure-IC Securyzr provides a complete range of security features while addressing all the state-of-the-art threats against embedded systems. Securyzr is customized according to each market's and client's specific requirements.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 31 to 60 out of 390

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