IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
D17IP04 Digital Filter
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP04 is a 3rd order cascade of integrators and comb, or differentiators,(CIC) digital filter.  In converts a single channel digital bit stream into a 16 bit output word with a 256 clock latency.  The design is optimized for area and power.

D17IP05 Current / Voltage Reference
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP05 is both a current and voltage reference. The current reference uses a negative TC resistor and VBE to reduce the temperature dependence. The output currents are 2µA and a programmable 200nA, 400nA, 800nA, or 1µA, sinking current. 

D17IP06 Current / Voltage Reference
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP06 is a digitally configurable current and voltage generator.  The reference includes a temperature compensated current and voltage source.  Output of the amplifiers can drive capacitive modes and settle with 16 bit accuracy within 500ns.

D17IP07 Under Voltage Detector
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP07 is an under voltage detector.  It has an enable signal to allow for detect control. It is designed to output an active low signal when the supply voltage drops below 2V for longer than 1 ms.

D17IP08 Interface
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP08 is a configurable 32 channel sample and hold input interface.  The input connects to a 8pF capacitor to ground through a selection multiplexer.  It can be configured as a daisy chain sample and hold circuit for delay line operations.

D17IP09 Transimpedance Amplifier
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP09 is an 8 channel bank of transimpedance amplifiers.  It has a programmable transimpedance gain.  It is internally compensated and supplies a virtual ground to both sink and source current at the input.

D17IP10 Oscillator
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP10 is a programmable RC oscillator with temperature compensated self bias.  The oscillator has 4 bit of input trim range to account for +/- 20% PVT variation.  The bas frequency of the oscillator is 1.6MHz. 

D17IP11 Current / Voltage Reference
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP11 is both a current and voltage reference with trimming capability.  The current reference uses a negative TC resistor and VBE to reduce the temperature dependence.  The output currents are 2µA and 1µA x2.

D17IP12 Analog Filter
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP12 is a 3rd order analog filter for video applications.  It has the architecture of a Tow-Thomas biquad.  The biquad is design for frequency tunning.  The implementation is an RC continuous time.  The cut off frequency is 6.5 MHz.

D17IP13 Voltage Driver
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP013D17IP13 is a video amplifier designed to drive 75 ohm coaxial cable.  It is configured in the inverting mode and allows minimal distortion for input signals up to 1Vp-p.  The output can be muted, gained or attenuated.

D17IP15 Voltage Regulator
Desert Microtechnology
1.00 µm
XC10
MP
GDSII
Schematic

D17IP15 is a voltage regulator with built in reference.  Has 5V low drop out regulator that can operate from 5.5V - 25V supply.  Has 14V regulator when the supply is > 25V.  Can be paired with D17IP16 to generate a voltage oscillator.

D17IP16 Oscillator
Desert Microtechnology
1.00 µm
XC10
MP
GDSII
Schematic

D17IP16 is a voltage oscillator at 500 kHz.  It requires 3 input reference voltages 1.064V, 1.275V and 0.762V.  These voltages can be generated with the D17IP15.  Output is to designed to drive on chip light loads.

Active Shield Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Attacks against digital circuits can be performed by directly tampering with the device's internal structure. Active Shield technology is designed to deter such intrusive attacks by placing a mesh over the sensitive parts of the circuit and monitor

CyberCPU Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

CyberCPU comprises technologies for detecting cyber-attacks targeted to hijack and take the control of the CPU. CyberCPU technologies are available as portable security features to be integrated in a targeted CPU architecture or as a ready to use IP Core.

Digital Sensor Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Cryptography attack can inject one or several faults into a device disrupting its functional behavior. The Digital Sensor detect various threats belonging to the family of Fault Injection Attacks (FIA) : Input clock frequency, Input Voltage, Temperature,

PUF Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

PUF IP Core is a secret key generation system based on Physically Unclonable Functions (PUF). This feature allows a real protection against the reverse-engineering techniques compared to traditional methods that store the key in non-volatile memory.

Scrambled Bus Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Scrambled Bus IP masks all data carried on the bus with random variables generated locally by cryptographic primitives. Features:
• On-the-fly masking and unmasking, no additional latency
• Transparent for bus masters and slaves
• etc.

 

 

Secure Boot Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Provides a secure root-of-trust with a high level of resistance against malevolent attacks, ensures integrity of the SoC security features and guarantees that the firmware is genuine. Optionally, it ensures the firmware’s confidentiality

Secure Clock Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure Clock IP core is intended to clock feed all desired hardware, creating a secure clock domain within the System on Chip host. ...it also fuzzes the relevant fault injection moment used by fault injection attacks.

Secure JTAG Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

The Joint Test Action Group (JTAG) is the IEEE1149.1 Standard Test Access Port (TAP) and Boundary-Scan Architecture. The TAP interface is a backdoor for hackers. Secure-IC offers a set of tools to secure the access to the device: Secure Test Access Port.

Secure Monitor Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure-IC Monitor gathers security events in real time and provides a high level interface to use security functions of the SoC. The Secure Monitor is a comprehensive toolbox, ideal for building a security policy and protecting sensitive assets.

Securyzr Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure-IC Securyzr provides a complete range of security features while addressing all the state-of-the-art threats against embedded systems. Securyzr is customized according to each market's and client's specific requirements.

TRNG Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

True Random Number Generators are used to generate statistically independent sets of bits for various applications such as One Time Pad cryptography, key generation, seeds for PRNGs, masks to protect an implementation against side-channel analysis.

Tunable Cryptography Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Symmetric Cryptography, Asymmetric Cryptography, Hash and MAC functions. Embedding the state-of-the-art countermeasure against high order side-channel attacks, Tunable Crypto IP allows you to reach the perfect balance between Security, Speed, and Area.

aopac02 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac02 is an internally compensated rail-to-rail input/output OpAmp.

aopac03 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac03 is an internally compensated general purpose OpAmp with N-MOS input and bipolar pnp output stage.

aopac04 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac04 is a internally compensated general purpose OpAmp with P-MOS input stage.

aopac05 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac05 is a fast internally compensated OpAmp with P-MOS input stage.

aopac06 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac06 is a high-gain, high load current CMOS OpAmp with N-MOS input and rail-to-trail output stage.

aopac07 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac07 is a general purpose internally compensated OpAmp with P-MOS input and source follower output stage.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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