IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
aopac06_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac06_3v3 is a general purpose internally compensated rail-to-rail input, rail-to-rail output CMOS operational amplifier (OpAmp).

aopac07_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac07_3v3 is a general purpose internally compensated rail-to-rail input, railt-to-rail ouput CMOS operational ampl;ifier (OpAmp).

aopac08_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac08_3v3 is a general internally compensated NMOS input, rail-to-rail output CMOS operational amplifier (OpAmp).

aopac09_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac09_3v3 is a general purpose internally compensated PMOS input, rail-to-rail output CMOS operational amplifier (OpAmp).

aopac03_5v Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V aopac03_5v is a general purpose internally compensated CMOS OpAmp with N-MOS input and rail-to-rail output stage.

aopac03_5v Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V aopac03_5v is a general purpose internally compensated CMOS OpAmp with P-MOS input stage and rail-to-rail output stage.

aopac03_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac03_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 1.1MHz and operates with VDD down to 1.2V.

aopac04_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac04_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 3.7MHz and operates with VDD down to 1.2V.

aopac09_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac09_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 162kHz.

aopac10_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac10_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 382kHz.

aopac11_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac11_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 1.5MHz.

aopac12_1v8 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aopac12_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 3.8MHz.

aopac01_3v3 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aopac01_3v3 is a general purpose internally compensated CMOS OpAmp with N-MOS input stage and rail-to-rail output stage. The speed, gain bandwidth, and the power consumption of the amplifier are set by means of a bias current.

aopac02_3v3 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aopac02_3v3 is a general purpose internally compensated CMOS OpAmp with P-MOS input stage and rail-to-rail output stage. The speed, gain bandwidth, and the power consumption of the amplifier are set by means of a bias current.

aopac03_3v3 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aopac03_3v3 is a general purpose internally compensated CMOS OpAmp with N-MOS input stage and rail-to-rail output stage. The speed, gain bandwidth, and the power consumption of the amplifier are set by means of a bias current.

aopac04_3v3 Operational Amplifier
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aopac04_3v3 is a general purpose internally compensated CMOS OpAmp with P-MOS input stage and rail-to-rail output stage. The speed, gain bandwidth, and the power consumption of the amplifier are set by means of a bias current.

D17IP02 Operational Amplifier
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP02 is a rail to rail unity gain CMOS amplifier.  It operates from 2V to 3.6V; has a quiescent current of 214uA; 50.2uV rms noise for a bandwidth of 10 Hz to 100kHz. Require an input current of 2uA; also pad compatible.

TI-RF-MUX Multiplexer
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-MUX is a 4-to-1 RF multiplexer designed with an internal current feedback output amplifier whose gain can be adjusted externally. There is a possibility of optional usage of two 4-to-1 devices as one 8-to-1 multiplexer. ESD protection provided.

MIXER Mixer
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_MIXER_CELLS. MIXER is a down conversion mixer based on a Gilbert cell topology. It should be biased by the RF bias cell.

LNA1 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA 1 is a low noise amplifier. It shoud be biased by the RF bias cell.

LNA2 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA2 is a low noise amplifier. It should be biased by the RF bias cell

LNA3 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA3 is a low noise amplifier with on-chip inductor. It should be biased by the RF bias cell.

LNA1 LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA1 is a broadband low noise amplifier. It should be bieased by the RF bias cell.

LNA2 LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA2 is a narrowband low noise amplifier. It should be biased by the RF bias cell.

D17IP08 Interface
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP08 is a configurable 32 channel sample and hold input interface.  The input connects to a 8pF capacitor to ground through a selection multiplexer.  It can be configured as a daisy chain sample and hold circuit for delay line operations.

DPIN Integrated Photodiode
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. DPIN_5050 and DPIN_50100 are fast photodiodes with a vertical PIN structure optimized forred light (660nm).

adrvc01 Driver
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. adrvc01 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output. The rising slope of the output signal can be controlled by means of a bias current.

adrvc01 Driver
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. adrvc01 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output (high-side switch). High input voltage makes the output go low (connected to ground). The rising slope of the output signal c

adrvc02 Driver
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. adrvc02 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output (low-side switch). High input voltage makes the output go low (connected to ground).

adrvc03 Driver
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. adrvc03 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output (high-side switch). High input voltage makes the output go low (connected to ground). The rising slope of the output signal c

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 181 to 210 out of 388

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