IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
PUF Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

PUF IP Core is a secret key generation system based on Physically Unclonable Functions (PUF). This feature allows a real protection against the reverse-engineering techniques compared to traditional methods that store the key in non-volatile memory.

Scrambled Bus Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Scrambled Bus IP masks all data carried on the bus with random variables generated locally by cryptographic primitives. Features:
• On-the-fly masking and unmasking, no additional latency
• Transparent for bus masters and slaves
• etc.

 

 

Secure Boot Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Provides a secure root-of-trust with a high level of resistance against malevolent attacks, ensures integrity of the SoC security features and guarantees that the firmware is genuine. Optionally, it ensures the firmware’s confidentiality

Secure Clock Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure Clock IP core is intended to clock feed all desired hardware, creating a secure clock domain within the System on Chip host. ...it also fuzzes the relevant fault injection moment used by fault injection attacks.

Secure JTAG Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

The Joint Test Action Group (JTAG) is the IEEE1149.1 Standard Test Access Port (TAP) and Boundary-Scan Architecture. The TAP interface is a backdoor for hackers. Secure-IC offers a set of tools to secure the access to the device: Secure Test Access Port.

Secure Monitor Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure-IC Monitor gathers security events in real time and provides a high level interface to use security functions of the SoC. The Secure Monitor is a comprehensive toolbox, ideal for building a security policy and protecting sensitive assets.

Securyzr Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure-IC Securyzr provides a complete range of security features while addressing all the state-of-the-art threats against embedded systems. Securyzr is customized according to each market's and client's specific requirements.

TRNG Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

True Random Number Generators are used to generate statistically independent sets of bits for various applications such as One Time Pad cryptography, key generation, seeds for PRNGs, masks to protect an implementation against side-channel analysis.

Tunable Cryptography Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Symmetric Cryptography, Asymmetric Cryptography, Hash and MAC functions. Embedding the state-of-the-art countermeasure against high order side-channel attacks, Tunable Crypto IP allows you to reach the perfect balance between Security, Speed, and Area.

aopac02 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac02 is an internal frequency-compensated CMOS operational amplifier with p-mos input stage

aopac03 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac03 is a fast internal frequency-compensated CMOS operational amplifier with p-mos input stage

aopac05 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac05 is a low power internal frequency-compensated CMOS operational amplifier with nmos input stage

aopac06 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac06 is an internal frequency-compensated CMOS operational amplifier with n-mos input stage

aopac07 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac07 is a fast internal frequency-compensated CMOS operational amplifier with n-mos input stage.

aopac09 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac09 is an internal frequency-compensated CMOS operational amplifier with p-mos input stage and rail-to-rail output stage.

aopac10 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac10 is an internal frequency-compensated CMOS operational amplifier with rail-to-rail input stage and rail-to-rail output stage.

acmpc01 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc01 is a low-power two-stage CMOS comparator with n-mos input stage and a CMOS-output stage.

acmpc03 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc03 is a low-power two-stage CMOS comparator with n-mos input stage and a CMOS-output stage.

acmpc04 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc04 is a two-stage CMOS comparator with p-mos input stage and a CMOS-output stage.

acmpc06 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc06 is a two-stage CMOS comparator with p-mos input stage and a CMOS-output stage.

acmpc10 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc10 is a CMOS comparator with rail-to-rail input stage and rail-to-rail output stage.

acmpc11 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc11 is low offset CMOS comparator with rail-to-rail input stage and rail-to-rail output stage.

abgpc01 Bandgaps
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abgpc01 is a Brokaw, general-purpose bandgap reference source with high resistive poly resistor. 

abgpc03 Bandgaps
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abgpc03 is a badgap reference with high resistive poly resistor.

abiac01 Bias
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abiac01 is a bias voltage source (VBP1, VBN1) which needs a bandgap cell for biasing.

abiac02 Bias
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abiac02 is a bias voltage source (VBP2, VBN2) which needs a bandgap cell for biasing.

abiac03 Bias
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abiac03 is a bias voltage source (VBP3, VBN3) which needs a bandgap cell for biasing.

ADC10 ADC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. ADC10 is a 10-bit analog-to-digital converter which utilizes successive approximation technique.

ADC8 ADC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. ADC8 is a 8-bit analog-to-digital converter which utilizes successive-approximation technique.

DAC10 DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC10 is a 10-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recommended at the

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 151 to 180 out of 390

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X-FAB will take no responsibility nor any liability whatsoever for the information or products offered or provided by the other IP suppliers at the database of the Intellectual Partner Network. X-FAB shall have no liability towards the customers for any use of and/or reliance of the products provided by the other IP suppliers at the database of the Intellectual Partner Network.

X-FAB's own IP is subject to a license agreement. X-FAB IP marked with “*” are part of the Master Kit or Master Kit Plus library. If you can not find the IP you are looking for, please contact the respective sales manager in your region. We continuously extend our libraries and offer a custom cell development service as well.