IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
TRNG Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

True Random Number Generators are used to generate statistically independent sets of bits for various applications such as One Time Pad cryptography, key generation, seeds for PRNGs, masks to protect an implementation against side-channel analysis.

Tunable Cryptography Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Symmetric Cryptography, Asymmetric Cryptography, Hash and MAC functions. Embedding the state-of-the-art countermeasure against high order side-channel attacks, Tunable Crypto IP allows you to reach the perfect balance between Security, Speed, and Area.

VREG1_8 Voltage Regulator
Suter IC-Design AG
0.18 μm
XC018
MP
GDSII
Schematic

Low power voltage regulator for 1.8V logic, requires only an external capacitor, available for XC018/XH018 MOS3LP and MOS5LP, different option available on request.

XTAL5M Crystal Oscillators
Suter IC-Design AG
0.18 μm
XC018
MP
GDSII
Schematic

Low power crystal oscillator for resonator with fast start-up, available for XC018/XH018 MOS3LP, including pads, different pads on request.

TI-RF-CMP Comparators
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-CMP is a low power CMOS RF comparator with 4 ns propagation delay and latch function. ESD protection provided.

TI-RF-DRV Driver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-DRV is a fully differential RF driver for differential signal processing applications. Common-mode level of differential outputs is adjustable that allows to shift easily the input signals for driving single-supply ADCs. ESD protection provided.

TI-RF-MUX Multiplexer
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-MUX is a 4-to-1 RF multiplexer designed with an internal current feedback output amplifier whose gain can be adjusted externally. There is a possibility of optional usage of two 4-to-1 devices as one 8-to-1 multiplexer. ESD protection provided.

TI-RF-Switch Analogue Switches
Thesys-Intechna
0.35 μm
XH035
VS
GDSII
Schematic

The TI-RF-Switch is a broad-band dual SPDT analog switch containing two single-pole double-throw switches. Used CMOS technology provides high isolation and low insertion loss at frequencies up to 1 GHz.

TI-16PI/150M ADC
Thesys-Intechna
0.18 μm
XT018
VS
GDSII
Schematic

TI-16PI/150M is a dual-channel fully differential 16-bit ADC with pipelined architecture optimized for high dynamic performance at sample rates up to 180 MSPS.

TI-Manchester Transceiver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-Manchester is a dual data bus transceiver designed for receiving CMOS/TTL Manchester II data, converting it and transmitting through a stepup transformer to the data bus...

TI-L500 Voltage Regulator
Thesys-Intechna
0.60 µm
XC06
PT
GDSII
Schematic

TI-L500 is a micro-power low dropout linear voltage regulator with fixed 5 V output voltage and input voltage of up to 40 V. ESD protection provided.

aopac01 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library

XC10: A_CELLS; A_CELLS_M1. aopac01 is an internally compensated general purpose OpAmp with P-MOS input and common-source output stage.

aopac02 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac02 is an internally compensated rail-to-rail input/output OpAmp.

aopac03 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac03 is an internally compensated general purpose OpAmp with N-MOS input and bipolar pnp output stage.

aopac04 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac04 is a internally compensated general purpose OpAmp with P-MOS input stage.

aopac05 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac05 is a fast internally compensated OpAmp with P-MOS input stage.

aopac06 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac06 is a high-gain, high load current CMOS OpAmp with N-MOS input and rail-to-trail output stage.

aopac07 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac07 is a general purpose internally compensated OpAmp with P-MOS input and source follower output stage.

acmpc01 Comparators
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. acmpc01 is a general purpose voltage comparator with P-MOS input and hysteresis.

acmpc03 Comparators
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. acmpc03 is a general purpose, low-consumption voltage comparator with N-MOS input.

acmpc04 Comparators
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. acmpc04 is a general purpose, low power voltage comparator with P-MOS input.

abgpc01 Bandgaps
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. abgpc01 is a bandgap reference with well resistors.

abgpc02 Bandgaps
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. abgpc02 is a bandgap reference with Poly2 resistors. The cell doesn’t include an output buffer.

abgpc03 Bandgaps
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. abgpc03 is a bandgap reference with Poly2 resistors. The cell doesn’t include an output buffer.

abiac01 Bias
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. abiac01 is a general purpose VTH - based current reference. The circuit forces a current of 2.4μA (approx.) to flow through P- or N-MOS transistor with a W/L ratio of 10μm/6μm.

abiac02 Bias
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. abiac02 is a general purpose weak inversion bias cell. The circuit forces a current of 250nA (approx.) to flow through P- or N-MOS transistors with a W/L ratio of 10μm/10μm.

achpc01 Charge Pumps
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. achpc01 is doubling charge pump 5V to 8.75V.

achpc02 Charge Pumps
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. achpc02 is a 4-stage Dickson charge pump originally designed for EEPROM.

arcoc01 Oscillator
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. arcoc01 is a 200kHz fixed frequency, current balancing RC oscillator with internal R and C.

arcoc02 Oscillator
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. arcoc02 is a 200kHz adjustable current balancing RC oscillator with internal R and C.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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