IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
IMMS SENT Transmitter Soft IP
IMMS GmbH
All Geometries
All Processes
PT
Verilog

Silicon-proven Verilog implementation of a flexible configurable SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. Up to 16-bit data from two independent sensors.

IPMS_430 Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

Compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features:
- 16 bit Risc CPU
- 7 address modes for source operands
- several low power features

IPMS_16CXX Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

8 Bit Microprocessor. The core IPMS_16CXX is a 8-bit microcontroller compatible to PIC 16CXX-family from Microchip.

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol used in low cost automotive networks. It enables cost efficient bus communication for applications where the bandwidth of CAN is not required. Support of LIN specification 2.2A

IPMS_CAN_FD Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

IPMS_CAN is a CAN bus controller that performs serial communication according to the CAN 2.0B and the CAN FD specification.It is compatible to ISO CAN FD andthe non-ISO (Bosch) CAN FD standard and has extended time stamp and time trigger capabilities.

Active Shield Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Attacks against digital circuits can be performed by directly tampering with the device's internal structure. Active Shield technology is designed to deter such intrusive attacks by placing a mesh over the sensitive parts of the circuit and monitor

CyberCPU Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

CyberCPU comprises technologies for detecting cyber-attacks targeted to hijack and take the control of the CPU. CyberCPU technologies are available as portable security features to be integrated in a targeted CPU architecture or as a ready to use IP Core.

Digital Sensor Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Cryptography attack can inject one or several faults into a device disrupting its functional behavior. The Digital Sensor detect various threats belonging to the family of Fault Injection Attacks (FIA) : Input clock frequency, Input Voltage, Temperature,

PUF Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

PUF IP Core is a secret key generation system based on Physically Unclonable Functions (PUF). This feature allows a real protection against the reverse-engineering techniques compared to traditional methods that store the key in non-volatile memory.

Scrambled Bus Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Scrambled Bus IP masks all data carried on the bus with random variables generated locally by cryptographic primitives. Features:
• On-the-fly masking and unmasking, no additional latency
• Transparent for bus masters and slaves
• etc.

 

 

Secure Boot Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Provides a secure root-of-trust with a high level of resistance against malevolent attacks, ensures integrity of the SoC security features and guarantees that the firmware is genuine. Optionally, it ensures the firmware’s confidentiality

Secure Clock Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure Clock IP core is intended to clock feed all desired hardware, creating a secure clock domain within the System on Chip host. ...it also fuzzes the relevant fault injection moment used by fault injection attacks.

Secure JTAG Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

The Joint Test Action Group (JTAG) is the IEEE1149.1 Standard Test Access Port (TAP) and Boundary-Scan Architecture. The TAP interface is a backdoor for hackers. Secure-IC offers a set of tools to secure the access to the device: Secure Test Access Port.

Secure Monitor Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure-IC Monitor gathers security events in real time and provides a high level interface to use security functions of the SoC. The Secure Monitor is a comprehensive toolbox, ideal for building a security policy and protecting sensitive assets.

Securyzr Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure-IC Securyzr provides a complete range of security features while addressing all the state-of-the-art threats against embedded systems. Securyzr is customized according to each market's and client's specific requirements.

TRNG Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

True Random Number Generators are used to generate statistically independent sets of bits for various applications such as One Time Pad cryptography, key generation, seeds for PRNGs, masks to protect an implementation against side-channel analysis.

Tunable Cryptography Security
Soft IP
Secure-IC
All Geometries
All Processes
PT
GDSII

Symmetric Cryptography, Asymmetric Cryptography, Hash and MAC functions. Embedding the state-of-the-art countermeasure against high order side-channel attacks, Tunable Crypto IP allows you to reach the perfect balance between Security, Speed, and Area.

adc10 ADC
X-FAB
0.80 µm
CX08
PT
Analog Library
Layout
Schematic

CX08A: Analog library. ADC10 is a 10-bit analog-to-digital converter which utilizes successive approximation technique.

adc8 ADC
X-FAB
0.80 µm
CX08
PT
Schematic
Layout
Analog Library

CX08A: Analog library. ADC8 is a 8-bit analog-to-digital converter which utilizes successive-approximation
technique.

dac8 DAC
X-FAB
0.80 µm
CX08
PT
Schematic
Layout
Analog Library

CX08A: Analog library. DAC8 is a 8-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recommen

dac10 DAC
X-FAB
0.80 µm
CX08
PT
Schematic
Layout
Analog Library

CX08A: Analog library. DAC10 is a 10-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recomm

AR32X3A ADC
Archband Labs Inc.
0.25 μm
FC025
PT
GDSII

AR32X3A is a 16-bit ADC for measurement purpose in 0.25µm node.

AR25X01 Other
Archband Labs Inc.
0.25 μm
FC025
PT
GDSII

AR25X01 is a 35mA LDO with the capless option in 0.25µm node

LNA1 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA 1 is a low noise amplifier. It shoud be biased by the RF bias cell.

LNA2 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA2 is a low noise amplifier. It should be biased by the RF bias cell

LNA3 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA3 is a low noise amplifier with on-chip inductor. It should be biased by the RF bias cell.

LCVCO2 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO2 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It is based on a cross-coupled bipolar transistor pair. It contains AC-coupled varactors and a special circuit technique for maintaining the D

LCVCO3 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other

RINGVCO1 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_VCO_CELLS. RINGVCO1 is a fully integrated VCO. It should be biased by the RF bias cell. It consists of a ringoscillator that is tuned by switching the delay chain between 2 and 4 delay stages. The transition between the two borders i

MIXER Mixer
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_MIXER_CELLS. MIXER is a down conversion mixer based on a Gilbert cell topology. It should be biased by the RF bias cell.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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X-FAB will take no responsibility nor any liability whatsoever for the information or products offered or provided by the other IP suppliers at the database of the Intellectual Partner Network. X-FAB shall have no liability towards the customers for any use of and/or reliance of the products provided by the other IP suppliers at the database of the Intellectual Partner Network.

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