209 entries
Published: May 2017

Automotive analog ICs are required to function without incidents over the expected product lifetime of 10 years and longer. This may equally apply to industrial and medical designs. While the goal of achieving zero incidences is the same, the actual operating conditions such as bias conditions and duty cycles, can vary considerably. The hot carrier injection (HCI) lifetime of high-voltage transistors is one of the critical areas that need to be considered.
X-FAB offers a suite of readily available process reliability documentation and support information including comprehensive Safe Operating Area (SOA) characterization to help you on your path towards achieving first-time-right designs. This webinar will provide an overview of the HCI reliability related material available for the 40 V and 60 V transistors of X-FAB’s 180 nm high-voltage SOI process (XT018). This is followed by a step-by-step guide of how to effectively utilize the given information to gauge the HCI lifetime based on a circuit example.


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Published: February 2017

More complex designs, shorter time to market and less time for engineering – these are the challenges IC designers are facing today. X-FAB addresses these to assist you in your design process. This 10th webinar of X-FAB’s first-time-right series will look at advancements made related to PDK features and design methodology since starting the series three years ago.
This webinar will showcase innovative PDK features and design methods which help you maximize design productivity and achieve first-time-right functional silicon.
Join this webinar and learn about new capabilities such as dummy structure generation flow for improved design robustness, simplified analysis of operating condition check results and advanced IP features for power/performance/area optimization.


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Published: December 2016

Negative Bias Temperature Instability (NBTI) is one of the critical degradation mechanisms in semiconductor device reliability that causes shift in the threshold voltage (Vth). However up until this decade being able to quantize and thoroughly understand the behavior of NBTI had still been in vain due to a recovery characteristics known as NBTI recovery. The first part of this paper shows a brief introductory to NBTI and the severe implications of NBTI recovery. 


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Published: October 2016

For a non-passivated thick Copper metallization on top of an AlCu stack a change in the reliability characterization and test strategy is necessary. Degradation mechanisms of thick Copper are partly different from thick Aluminium.


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Published: October 2016

The best performance of a semiconductor component will not necessarily lead to success if it cannot be manufactured with a suitable quality. In order to achieve highest quality at reasonable costs, very challenging solutions need to be developed and integrated into semiconductor technologies. To enable advanced analog/mixed-signal products for a safe application in harsh environments such as automotive or avionics and for consumer markets, built-in robustness is paramount. The webinar will show the requirements, solutions and consequences for X-FAB’s semiconductor manufacturing processes and their architecture. Important aspects such as process and primitive device selection, process capability, primitive device reliability and chip-package interaction will be addressed. Finally, guidelines for the development and qualification of robust products and a safe launch process will be presented.


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Published: October 2016

Glass frit wafer bonding remains a very attractive process for industrial applications. The main benefit is that the glass frit is an active bonding layer, which planarizes surface roughness and topography up to the direct sealing of metal lines at the bonding interface. This allows very simple process integration. 


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Published: October 2016

Semiconductor direct wafer bonding is a widely used process for fabricating 3-dimensional structures, especially engineered substrates such as SOI wafers or cavity wafers with and without insulating layers at the bonding interface. The investigations described here concern cavity SOI wafers without insulating layers, as used for discrete and integrated pressure sensors.


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Published: September 2016

Silicon nitride (SiNx) is commonly used as the dielectric or insulator material for metal-insulator-metal (MIM) capacitors. The deposition of SiNx can be performed using plasma-enhanced chemical vapor deposition (PECVD) method with different deposition parameters by changing individually the SiH4 flow rates, NH3 flow rates, RF power, substrate temperature, etc. Time-dependent dielectric breakdown (TDDB) is the most important reliability test item to check the intrinsic performance of the MIM capacitor dielectrics. 


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Published: September 2016

The typical via layout in AlCu-metallizations with tungsten via is cylindrical. Common vias have a size as small as possible. More challenging application, temperature and mission profiles require higher robustness of a metallization. Via arrays of small common vias are in use to transfer higher currents. But the typical via array layout is not the best layout for applications which are faced to high mechanical stress. 


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Published: September 2016

The formation of voids in metal layers upon stress-induced migration is a well-known defect mechanism in integrated circuits. This phenomenon largely accelerates with increasing ambient temperature. Consequently, the occurrence and the growth of voids result in an increased electrical resistivity which once more leads to an acceleration of the growth rate highly impacting the reliability and the life span of the device. Technological improvements aim at the minimization of stress induced voiding. However, for understanding and optimization of process related factors nondestructive methods for screening and systematic monitoring of the void formation e.g. during stepwise reliability testing are required.


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