Abstract—This paper, presents a physically-based matching model that includes mismatch fluctuations in HiSIM_HV MOSFET model. Analytical expressions of the variation associated to the threshold voltage, current factor, and drift region resistor were developed and added to the compact model. The proposed model predicts accurately the mismatch in the drain current over a wide operating range and uses only three model parameters. This was validated through Monte Carlo simulations compared to experimental measurements on several device classes from X-FAB 0.18 um processes. The results of the drain current mismatch, the standard deviation of threshold voltage, and the standard deviation of the current factor are presented here and show good agreement between measurements and simulations.

Full physical 3D TCAD are often limited to smaller geometries. As the simulation domain increases in size an emulation approach is often taken with lower accuracy [1]. The 375V partial SOI LDNMOS is a large device with a complex, high aspect ratio, multi-region deep trench isolation (DTI) termination structure combined with the HW diode. Additionally, the device has a multitude of small floating silicon regions and a significant amount of silicon/oxide interfaces, coupled with floating field plates. As such, a complete 3D simulation was impossible. A new methodology of domain decomposition using Silvaco’s Victory 3D TCAD [3] has been introduced. The device is broken down into several elements, small enough to enable usage of Monte Carlo Implantation and physical annealing models. After the process simulation, the elements are then joined and re-meshed for device simulation.

A partial silicon on insulator (PSOI) is a widely recognized technology suitable for high-voltage (HV) architectures for power integrated circuits (PICs). Despite the added process complexity compared with SOI reduced surface field (RESURF), this technology offers a wider range of voltage ratings due to the action of the depletion layer in the handle wafer (HW), reduced parasitic capacitances
due to the extra volume of the depletion region in the HW, and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-D designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of HV integrated circuits (HVICs) where low ON-state resistance and reduced self-heating are essential requirements. This work presents
a PSOI technology platformwith the voltage ratings ranging from 45 to 400 V while providing low ON-state resistance, good hot carrier injection stability, as well as electrostatic discharge (ESD) capability of the HV devices. For example, for a 375-V rated laterally diffused MOSFET (LDMOSFET), this technology achieves an ON-state resistance of 1435mmm2, an over 50% improvement comparedwith the
state-of-the-artSOI technologies whilemaintaining competitive reliability.

Abstract: Several approaches for close integration of GaN power switches with silicon based CMOS logic are subject of technical evaluations and academic discussions. There is a common motivation for the different integration approaches to position gate driver logic and the power gate as close as possible to reduce parasitics and enhance efficiency. While academic research is and has to be done in all fields further industrial development can only occur within commercially promising areas. Therefore commercial boundary conditions impose economic limits to the usability of the different integration approaches to certain potential approaches. Basic cost estimation models for costs per wafer and costs per chip for different integration approaches are checked with real application driven IC examples.

Abstract -- HV integrated lateral IGBTs are investigated as an attractive alternative to MOSFETs in integrated high-voltage (up to 230 V), low-power (5 - 500 mW) converters. A performance comparison of SJ-LIGBTs and SJ-MOSFETs is applied to define the design constraints and, consequently, to implement an optimized one-step power conversion topology with both device types. Measurement results of the topology with SJ-LIGBT show an up to 4.2 % higher efficiency in comparison to the SJ-MOSFET converter at 20.4 % smaller power-switch size.

Abstract—This work reports on the progress of the heterointegration of GaN-HEMTs on CMOS wafers by micro-transferprinting (µTP). 200 V and 600 V class device types are successfully transferred from a GaN-on-Si source wafer to a processed CMOS target wafer. Technologies and process steps of the micro-transferprinting are briefly discussed. Both device types are characterized, before micro-transfer-printing on the original Si substrate, and after micro-transfer-printing on the CMOS wafer. The comparison discloses the impact of the micro-transfer-print process on the electrical performance.

Partial SOI (PSOI) is revisited as a suitable High Voltage (HV) architecture for Power Integrated Circuits (PICs). The added process complexity compared to SOI RESURF is offset by the better heat conduction due to thinner BOX, the wider voltage range capability and the reduced parasitic capacitance to the Handle Wafer (HW). The new proposed platform technology is therefore particularly relevant to the manufacturing of high voltage integrated circuits (HVICs) where low Ron, fast switching and reduced self-heating are essential. This work reports on the extension of a 200V PSOI process to 400V while providing competitive Ron and low HCI degradation.