Abstract —Lateral Schottky barrier diodes were implemented in a thin body RF-SOI platform with CoSi2.  Both n-type and p-type device constructions were explored with various geometries and configurations.  Devices were modeled with TCAD, characterized, and their respective performance assessed.  In a demonstration in the targeted application as a zero bias detector, results of output voltage sensitivity to RF input power levels between –20 to 0dBm at frequencies up to 30 GHz are supportive to achieving mmW integrated circuits. 

Keywords — Schottky barrier diode, integrated, RF-SOI, zero bias detector, mmW

Abstract—This paper presents the Radio Frequency (RF) circuit design and characterization of a Single Pole Double Throw (SPDT) switch. The switch is realized in a Gallium Nitride (GaN)/RF-SOI heterogeneous technology using “Micro-transferprinting”. The measured insertion loss and isolation are respectively below 0.65 dB and -12.7 dB up to 6 GHz. The large signal characterization using a continuous wave shows a hard breakdown at 36 dBm. On the other hand, the pulsed large signal measurement shows a 1dB input compression point of 48 dBm which meets the targeted value. This result confirms that the hard breakdown in CW is due to heat accumulation in the GaN. To address this issue, a heat evacuation technique for future hardware iteration is proposed. This heat evacuation technique should allow to achieve a CP1 of 48 dBm. And so, fully benefit from the advantages from both GaN and RF-SOI technologies on the same chip. 

Keywords—GaN, RF-SOI, Heterogeneous technology, Switch.

This paper presents a novel 3D EM multi-technology simulation flow applied to the Micro-Transfer Printing (MTP) heterogeneous integration technique between GaN and RF-SOI. A modular approach is proposed which relies on the two technology PDKs, the definition of a Cu-RDL technology and an assembly library. This flow addresses the intricate nature of the conformal RDL between the two technologies. Additionally, it offers a complete traceability, physical verification as well as EM simulation environment. The flow is verified with two MTP demonstrators, a CPW transmission line and a DC-6GHz SPDT switch. A good hardware/model correlation is observed which validate the proposed flow.

Abstract—We present in this study a novel way to determine the three-dimensional (3D) temperature field of a Radio Frequency Silicon On Insulator (RF SOI) electronic chip, using several resistance temperature detectors (RTDs) embedded at different locations of the chip. The RTDs are designed and placed at different locations to experimentally obtain the temperature at key locations of the chip enabling the calibration of a multiphysical numerical model that provides the 3D temperature field in the whole chip under operating conditions. The obtained results provide useful insights on the role of different parameters (e.g. used materials properties, heat source power, substrate, boundary conditions, etc.) to engineers interested in the modelling and optimization of heat transport and thermal management of electronic chips for RF applications.