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Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
aregc01 Voltage Regulator
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aregc01 is a 5V / 3.3V positive voltage linear regulator for up to 10 mA load current.

aregc02 Voltage Regulator
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aregc02 is a 2.4V / 3.3V positive voltage switching regulator for on-chip loads and up to 10 mA load current.

AV2102 600mA Buck Voltage Regulator
Aivaka
0.60 µm
XC06
PT
GDSII

DC/DC regulator.

aregc01 Voltage Regulator
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS_HV. For MOS module only. aregc01 is a 5V/3.3V linear voltage regulator for up to 20mA load current. The regulator is powered viz its high voltage input.

aregc02 Voltage Regulator
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. aregc02 is a 12V/3.3V linear voltage regulator for up to 20mA load current. The regulator is powered via its high-voltage input.

AV2110 600mA Buck Voltage Regulator
Aivaka
0.60 µm
XC06
PT
GDSII

DC/DC Buck Regulator with 0% to 100% duty cycle.

QCBGB10_35X Voltage Regulator
Bias
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Bandgap Voltage Reference and Current Bias Cell.

VREG1_8 Voltage Regulator
Suter IC-Design AG
0.18 μm
XC018
MP
GDSII
Schematic

Low power voltage regulator for 1.8V logic, requires only an external capacitor, available for XC018/XH018 MOS3LP and MOS5LP, different option available on request.

aregc01_3v3 Voltage Regulator
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC01801_3v3 is a 3.3V/1.8V linear voltage regulator for up to 20mA load current and internal bandgap reference. The regulator is implimented as a macro cell that fits into the core-limited I/O ring.

CM1112ae Voltage Regulator
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

General purpose linear voltage regulator. The circuit generates a 3.3V output voltage from an unregulated input voltage ranging from 5V to 30V. It features short circuit protection and 5mA output current capability.

aregc01_3v3 Voltage Regulator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aregc01_3v3 is a 3.3v/1.8V linear voltage regulator for up to 20mA load current and internal bandgap reference. The regulator is implemented as macro cell that fits into the core-limited I/O ring.

TI-L500 Voltage Regulator
Thesys-Intechna
0.60 µm
XC06
PT
GDSII
Schematic

TI-L500 is a micro-power low dropout linear voltage regulator with fixed 5 V output voltage and input voltage of up to 40 V. ESD protection provided.

LCVCO2 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO2 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It is based on a cross-coupled bipolar transistor pair. It contains AC-coupled varactors and a special circuit technique for maintaining the D

LCVCO3 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other

RINGVCO1 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_VCO_CELLS. RINGVCO1 is a fully integrated VCO. It should be biased by the RF bias cell. It consists of a ringoscillator that is tuned by switching the delay chain between 2 and 4 delay stages. The transition between the two borders i

avcoc01_3v3 VCO
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V avcoc01_3v3 is a voltage controlled oscillator (VCO).

TI-Manchester Transceiver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-Manchester is a dual data bus transceiver designed for receiving CMOS/TTL Manchester II data, converting it and transmitting through a stepup transformer to the data bus...

SUPI4 Soft IP
MAZeT Gmbh
All Geometries
All Processes
VS
VHDL

Interbus Slave Controller Version 4. Visit MAZeT website for datasheet.

EnDAT2.2 Soft IP
MAZeT Gmbh
All Geometries
All Processes
VS
VHDL

Sensor Interface used in positioning systems. Visit MAZet website for datasheet.

IPMS_430 Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

Compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features:
- 16 bit Risc CPU
- 7 address modes for source operands
- several low power features

IPMS_16CXX Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

8 Bit Microprocessor. The core IPMS_16CXX is a 8-bit microcontroller compatible to PIC 16CXX-family from Microchip.

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol used in low cost automotive networks. It enables cost efficient bus communication for applications where the bandwidth of CAN is not required. Support of LIN specification 2.2A

IMMS SENT Transmitter Soft IP
IMMS GmbH
All Geometries
All Processes
PT
Verilog

Silicon-proven Verilog implementation of a flexible configurable SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. Up to 16-bit data from two independent sensors.

IPMS_CAN_FD Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

IPMS_CAN is a CAN bus controller that performs serial communication according to the CAN 2.0B and the CAN FD specification.It is compatible to ISO CAN FD andthe non-ISO (Bosch) CAN FD standard and has extended time stamp and time trigger capabilities.

aporc01 Power on Reset
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aporc01 is a digital power-on-reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. After the threshold has been reached, the POR signals turns low. A delay of

aporc02 Power on Reset
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aporc02 is a digital power-on-reset circuit. PORB output is kept low as long as the supply voltage is below the POR threshold voltage. PORB signal is generated on both rising and falling edges of the supply voltage. During power

aporc04 Power on Reset
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aporc04 is a digital power-on-reset circuit. PORB output is kept low as long as the supply voltage is below the high POR threshold voltage. PORB signal is generated on both rising and falling edges of the supply voltage. During

apogc01 Power on Reset
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. apogc01 is a general purpose, power good detector. A power good signal (active high) is generated as long as the supply voltage at the VDDA pin lies within the 4.5V - 5.5V limits. When the supply voltage is beyond the either low

aporc01 Power on Reset
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is bellow the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay of few microse

aporc02 Power on Reset
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept high as long as the supply voltage is bellow the high threshold

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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