IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
arcoc08 Oscillator
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 arcoc08 is a 10MHz low-power oscillator with internal R and C.

arcoc09 Oscillator
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 arcoc09 is a 20MHz low-power oscillator with internal R and C.

axtoc01 Crystal Oscillators
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 axtoc01 is a 32kHz crystal oscillator for 3.5 to 5.5V supply voltage range. An external quartz has to be connected to XTALIN and XTALOUT pins.

axtoc02 Crystal Oscillators
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 axtoc02 is a 1...4MHz crystal oscillator for supply voltage range from 3.5 to 5.5V. An external quartz crystal as to be connected to XTALIN and XTALOUT pins.

axtoc03 Crystal Oscillators
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 axtoc03 is a 1...6MHz crystal oscillator for supply voltage range from 3.3 to 5.5V. An external quartz crstal has to be connected to XTALIN and XTALOUT pins.

aporc01 Power on Reset
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low.

aporc02 Power on Reset
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 aporc02 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on both the rising and failing edge of the supply voltage. During power-on, POR outputs is kept high as long as the supply voltage is below the threshold voltage.

achpc01 Charge Pumps
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 achpc01 is a doubling charge pump 3.3V => 5.6V.

AV2102 600mA Buck Voltage Regulator
Aivaka
0.60 µm
XC06
PT
GDSII

DC/DC regulator.

AV2110 600mA Buck Voltage Regulator
Aivaka
0.60 µm
XC06
PT
GDSII

DC/DC Buck Regulator with 0% to 100% duty cycle.

QCADB5_35X Other
QualCore Logic, Inc.
0.35 μm
XH035
PT
GDSII
Schematic

Connectivity IP. This is a product chip.

AR32X3A ADC
Archband Labs Inc.
0.25 μm
FC025
PT
GDSII

AR32X3A is a 16-bit ADC for measurement purpose in 0.25µm node.

AR25X01 Other
Archband Labs Inc.
0.25 μm
FC025
PT
GDSII

AR25X01 is a 35mA LDO with the capless option in 0.25µm node

ADC12DR ADC
A3PICs GmbH
0.60 µm
XB06
PT
GDSII

The ADC12DR is a SAR-based low-power ADC with a 12bit resolution. Its fully differential input stage features a rail-to-rail input range. At a sampling rate of 2MS/s a power consumption of only 10mW is attained applying a 5V power suppl

Sub 1dB LNA+mixer LNA
Mixer
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

LNA  and optional mixer based on XH035 process. Measured noise figure below 1dB including mixer. Described in a paper on the web site.  The techniques are readily applied to other processes.

Low Power DDS Other
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

Novel aproach to Direct Digital Synthesis, using a voltage-ladder reference. Accuracy is achieved by using a full resistor ladder array, so bit size equivalent to 12 bits has been shown. Prototypes using an 8 bit system are available on

Analogue SSB Chip Other
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

Very low power (3V, 25uA) 90 degree analogue phase shifter for SSB encoding/decoding. A full description is on the web site, with all measurements.

IPMS_430 Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL

16 Bit Microcontroller

The core IPMS_430 is compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features are

- 16 bit Risc CPU

- 7 address modes for source operands

- 4 a

IPMS_16CXX Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL

8 Bit Microprocessor.

The core IPMS_16CXX realizes a to the PIC 16CXX-family of the firm Microchip compatible 8-bit microcontroller Important features are:

- 8-bit arithmetic (addition, subtraction, logical operations, bit manipulation)

- to 64 k i

IPMS_16550 Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

The UART-core IPMS_16550 realize the functionality of an serial interface.

Features:

Data rates, data formats and interrupt events are programmable

compatible to UART 16550

high flexibility in different uses

IPMS_CAN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

CAN-Controller

Features

implementation of the Basic CAN specification

no generated Overload Frames

receiving and transmitting of both identifiers (CAN specification 2.0B)

programmable data rate up to 1 Mbit/s

programmable

IPMS_IIC Other
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

The core realized the I²C-bus protocol

Features:

Master and receive mode realized

Bus node address and data transmission rate are programmable

8 Bit data interface to the controller

All I²C function are implemented

Core is multimasterable   

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol

Features

Support of LIN specification 2.0

Programmable data rate between 1 Kbit/s and 20 Kbit/s

4 MHz clock frequency

8-byte data buffer

8-bit host controller interface

Support of

abgpc01_3v3 Bandgaps
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V abgpc01 is a general purpose low-power bandgap reference with N-well resistors.

abgpc02_3v3 Bandgaps
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V abgpc02 is a general purpose low-power bandgap reference with rnp1 resistors

abgpc03_3V3 Bandgaps
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V abgpc03 is a low-voltage bandgap reference with N-well resistors.

aopac03_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac03_3v3 is a general purpose internally compensated rail-to-rail input, rail-to-rail output CMOS operational amplifier (OpAmp). The speed, gain bandwidth, and the power consumption of the amplifier are set by means of a bias curren

aopac06_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac06_3v3 is a general purpose internally compensated rail-to-rail input, rail-to-rail output CMOS operational amplifier (OpAmp).

aopac07_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac07_3v3 is a general purpose internally compensated rail-to-rail input, railt-to-rail ouput CMOS operational ampl;ifier (OpAmp).

aopac08_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac08_3v3 is a general internally compensated NMOS input, rail-to-rail output CMOS operational amplifier (OpAmp).

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 241 to 270 out of 369

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