IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
abiac02 Bias
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. abiac02 is a general purpose VTH-based bias cell, a plain substitute for abiac01. The circuit forces a current of 2µA (approx.) to flow through PMOS with W/L ratio of 6µm/6µm and NMOS with W/L ration

abiac03 Bias
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. abiac03 is a general purpose weak inversion bias cell. The circuit forces a current of 200nA (approx.) to flow through PMOS with W/L ratio of 6µm/12µm and NMOS with W?L ration of 6µm/20µm.

acsoc01 Bias
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. acsoc01 is a general purpose current source. The circuit drives a current of 2µA (approx.) at each of its outputs.

acsoc02 Bias
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. acsoc02 is a general purpose current source. The circuit drives a current of 2µA (approx.) at each of its outputs. No reference voltage is necessary.

abiac04 Bias
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. abiac04 is a high voltage bias cell. The circuit forces a current of 2µA (approx.) to flow through PHV with W/L ratio of 8µm/12µm and NHV with W/L ratio of 8µm/14µm.

BIAS Bias
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: BIAS Library: RF_BIAS_CELLS. BIAS is a bias cell intended for use with the various RF building blocks. It is based on a bandgap reference and voltage-to-current converters. Current biasing is preferable because of the higher immunity to interferenc

abiac01_3v3 Bias
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V abiac01_3v3 is a general purpose bias cell. The circuit forces a current of 200nA (approx.) to flow through PMOS with W/L ratio of 8µm/10µm and NMOS with W/L ratio of 4µm/20µm.

abiac02_3v3 Bias
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V abiac02_3v3 is a general purpose bias cell. The circuit forces a current of 2µA (approx.) to flow through PMOS with W/L ratio of 10µm/4µm and NMOS with W/L ratio od 6µm/12µm.

abiac03_3v3 Bias
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V abiac03_3v3 is a general purpose bias cell. The circuit forces a current of 10µA (approx.) to flow through PMOS with W/L ratio of 24µm/2µm and NMOS with W/L ratio od 14µm/6µm.

abiac06_5v Bias
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 5V abiac06_5v is a general purpose bias cell. The circuit forces a current of 10µA (approx.) to flow through PMOS with W/L ratio of 24µm/3µm and NMOS with W/L ratio of 10µm/4µm.

abiac07_5v Bias
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 5V abiac07_5v is a general purpose bias cell. The circuit forces a current of 2µA (approx.) to flow through PMOS with W/L ratio of 10µm/6µm and NMOS with W/L ratio of 10µm/12µm.

abiac01 Bias
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XTabiac01 is a general purpose low-current bias cell. the circuit forces a current of 200nA (approx.) to flow through P- or N- MOS with W/L ratio of 10µm/12µm.

abiac02 Bias
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 abiac02 is a general purpose bias cell. The circuit forces a current of 2µA (approx.) to flow through P- or N- MOS with W/L ratio of 10µm/10µm.

abiac03 Bias
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 abiac03 is a general purpose biac cell. The circuit forces a current of10µA (approx.) to flow through P- or N- MOS with W/L ratio of 10µm/6µm.

abiac05 Bias
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 abiac05 is a general purpose VTH - based bias cell, a cheaper substitute for abiac02. The circuit forces a current of 2µA (approx.) to flow through P- or N- MOS with W/L ratio of 10µm/10µm.

abiac06 Bias
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 abiac06 is a general purpose VTH - based bias cell, a cheaper substitute for abiac03. The circuit forces a current of 10µA (approx.) to flow through P- or N- MOS with W/L ration of 10µm/6µm.

abiac06_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V abiac06_1v8 is a general purpose low voltage (down to 1.2V) bias cell. The circuit forces a current of 2µA (approx.) to flow through N-MOS with W/L ratio of 20µm/8µm.

abiac08_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8Vabiac08_1v8 is a general purpose low voltage (down to 1.2V) bias cell. The circuit forces a current of 10µA (approx.) to flow through N-MOS with W/L ratio of 40µm/60µm.

abiac01_3v3 Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V abiac01_3v3 is a general purpose bias cell. the circuit provides bias voltages so that a current of 200nA (approx.) to flow through PMOS with W/L ration of 8µm/10µm and NMOS with W/L ratio of 4µm/20µm.

abiac02_3v3 Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V abiac02_3v3 is a general purpose bias cell. the circuit provides bias voltages so that a current of 2µA (approx.) to flow through PMOS with W/L ration of 10µm/4µm and NMOS with W/L ratio of 6µm/12µm.

abiac03_3v3 Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V abiac03_3v3 is a general purpose bias cell. the circuit provides bias voltages so that a current of 10µA (approx.) to flow through PMOS with W/L ration of 24µm/2µm and NMOS with W/L ratio of 14µm/6µm.

achpc01 Charge Pumps
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. achpc01 is doubling charge pump 5V to 8.75V.

achpc02 Charge Pumps
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. achpc02 is a 4-stage Dickson charge pump originally designed for EEPROM.

achpc01 Charge Pumps
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. achpc01 is a doubling charge pump 3.3V -> 5.7V. All capacitors are internal.

achpc01 Charge Pumps
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 achpc01 is a doubling charge pump 3.3V => 5.6V.

acmpc01 Comparators
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. acmpc01 is a general purpose voltage comparator with P-MOS input and hysteresis.

acmpc03 Comparators
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. acmpc03 is a general purpose, low-consumption voltage comparator with N-MOS input.

acmpc04 Comparators
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. acmpc04 is a general purpose, low power voltage comparator with P-MOS input.

acmpc01 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc01 is a low-power two-stage CMOS comparator with n-mos input stage and a CMOS-output stage.

acmpc03 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc03 is a low-power two-stage CMOS comparator with n-mos input stage and a CMOS-output stage.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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