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Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
aporc03_3v3 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aporc02_3v3 is a Power-on-Reset circuit. Reset signal are generated on power-on and power-off transitions. Both high and low (POR and PORB) reset signals are available.

aregc01_3v3 Voltage Regulator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aregc01_3v3 is a 3.3v/1.8V linear voltage regulator for up to 20mA load current and internal bandgap reference. The regulator is implemented as macro cell that fits into the core-limited I/O ring.

atmpc01_3v3 Other
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V atmpc01_3v3 is a high-temperature alarm cirsuit. When the chip temperature rises over the high threshold temperature (133°C approx) an OVT (active high) signal is activated.

EnDAT2.2 Soft IP
MAZeT Gmbh
All Geometries
All Processes
VS
VHDL

Sensor Interface used in positioning systems. Visit MAZet website for datasheet.

SUPI4 Soft IP
MAZeT Gmbh
All Geometries
All Processes
VS
VHDL

Interbus Slave Controller Version 4. Visit MAZeT website for datasheet.

IPMS_AES Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Cryptographie core according to AES standard

Features

High processing speed of 100 Mbit / s (128 bit key, 25 MHz).

Same speed for coding and decoding.

Key widths of 128, 192 and 256 bit are implemented

120 kGates.

IPMS_DES Other
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Cryptographic Processor Core for the DES Algorithm

The hardware realizes a flexible DES core to encrypt and decrypt data with high speed. The encryption /decryption of a 64 bit data set takes 16 clock periods.

IPMS_ECC Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Processor core for Elliptic Curve Cryptography

IEEE-Standard 1076-1993 compliant synthesizable VHDL model for utiliza¬tion as macro cell in ASIC and FPGA designs

Diffie-Hellman key exchange proto¬col exists

Implementation of other proto¬cols based o

IPMS_IRHSP Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL

IrDA Hight Speed Protocl Stack

Features:

Complete IrDA protocol stack (IrPHY, Framer, IrLAP, IrLMP, IAS, TinyTP, IrCOMM, IrOBEX)

Primary and secondary function (scalable)

Data rates from 9.6 kbit / s - 16 Mbit / s (scalable)

IR remote control functio

IPMS_RSA Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
Verilog
VHDL

Cryptographic Processor Core for Public Key En¬cryption

processor core for modulo n multiplication and exponentiation (RSA) with high speed and high bit sizes

Data rates (for a 1024 bit system at 25 MHz clock frequency)

1024 bit RSA up to 10 kbit/s

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 361 to 370 out of 370

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The Intellectual Partner Network is a web database provided by X-FAB in cooperation with selected partners. Both X-FAB and a variety of different IP supplier offer their IP to customers using X-FAB’s foundry process. X-FAB will support customers to get in direct contact with the relevant IP supplier.

X-FAB will take no responsibility nor any liability whatsoever for the information or products offered or provided by the other IP suppliers at the database of the Intellectual Partner Network. X-FAB shall have no liability towards the customers for any use of and/or reliance of the products provided by the other IP suppliers at the database of the Intellectual Partner Network.

X-FAB's own IP is subject to a license agreement. X-FAB IP marked with “*” are part of the Master Kit or Master Kit Plus library. If you can not find the IP you are looking for, please contact the respective sales manager in your region. We continuously extend our libraries and offer a custom cell development service as well.