IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
aregc02 Voltage Regulator
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aregc02 is a 2.4V / 3.3V positive voltage switching regulator for on-chip loads and up to 10 mA load current.

adrvc01 Driver
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. adrvc01 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output. The rising slope of the output signal can be controlled by means of a bias current.

atmpc01 X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. atmpc01 is a high-temperature detector. An OVERT output signal (active low) is generated when the chip temperature rises above 140 °C (approx.).

atmpc02 X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. atmpc02 is a high-temperature detector. An OVERT output signal (active low) is generated when the chip temperature rises above 160 °C (approx.).

SUPI4 Soft IP
MAZeT Gmbh
All Geometries
All Processes
VS
VHDL

Interbus Slave Controller Version 4. Visit MAZeT website for datasheet.

EnDAT2.2 Soft IP
MAZeT Gmbh
All Geometries
All Processes
VS
VHDL

Sensor Interface used in positioning systems. Visit MAZet website for datasheet.

IPMS_430 Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

Compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features:
- 16 bit Risc CPU
- 7 address modes for source operands
- several low power features

IPMS_16CXX Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

8 Bit Microprocessor. The core IPMS_16CXX is a 8-bit microcontroller compatible to PIC 16CXX-family from Microchip.

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol used in low cost automotive networks. It enables cost efficient bus communication for applications where the bandwidth of CAN is not required. Support of LIN specification 2.2A

IMMS SENT Transmitter Soft IP
IMMS GmbH
All Geometries
All Processes
PT
Verilog

Silicon-proven Verilog implementation of a flexible configurable SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. Up to 16-bit data from two independent sensors.

IPMS_CAN_FD Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

IPMS_CAN is a CAN bus controller that performs serial communication according to the CAN 2.0B and the CAN FD specification.It is compatible to ISO CAN FD andthe non-ISO (Bosch) CAN FD standard and has extended time stamp and time trigger capabilities.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 361 to 371 out of 371

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