IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
IPMS_430 Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL

16 Bit Microcontroller

The core IPMS_430 is compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features are

- 16 bit Risc CPU

- 7 address modes for source operands

- 4 a

IPMS_16CXX Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL

8 Bit Microprocessor.

The core IPMS_16CXX realizes a to the PIC 16CXX-family of the firm Microchip compatible 8-bit microcontroller Important features are:

- 8-bit arithmetic (addition, subtraction, logical operations, bit manipulation)

- to 64 k i

IPMS_16550 Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

The UART-core IPMS_16550 realize the functionality of an serial interface.

Features:

Data rates, data formats and interrupt events are programmable

compatible to UART 16550

high flexibility in different uses

IPMS_AES Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Cryptographie core according to AES standard

Features

High processing speed of 100 Mbit / s (128 bit key, 25 MHz).

Same speed for coding and decoding.

Key widths of 128, 192 and 256 bit are implemented

120 kGates.

IPMS_CAN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

CAN-Controller

Features

implementation of the Basic CAN specification

no generated Overload Frames

receiving and transmitting of both identifiers (CAN specification 2.0B)

programmable data rate up to 1 Mbit/s

programmable

IPMS_DES Other
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Cryptographic Processor Core for the DES Algorithm

The hardware realizes a flexible DES core to encrypt and decrypt data with high speed. The encryption /decryption of a 64 bit data set takes 16 clock periods.

IPMS_ECC Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Processor core for Elliptic Curve Cryptography

IEEE-Standard 1076-1993 compliant synthesizable VHDL model for utiliza¬tion as macro cell in ASIC and FPGA designs

Diffie-Hellman key exchange proto¬col exists

Implementation of other proto¬cols based o

IPMS_IIC Other
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

The core realized the I²C-bus protocol

Features:

Master and receive mode realized

Bus node address and data transmission rate are programmable

8 Bit data interface to the controller

All I²C function are implemented

Core is multimasterable   

IPMS_IRHSP Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL

IrDA Hight Speed Protocl Stack

Features:

Complete IrDA protocol stack (IrPHY, Framer, IrLAP, IrLMP, IAS, TinyTP, IrCOMM, IrOBEX)

Primary and secondary function (scalable)

Data rates from 9.6 kbit / s - 16 Mbit / s (scalable)

IR remote control functio

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol

Features

Support of LIN specification 2.0

Programmable data rate between 1 Kbit/s and 20 Kbit/s

4 MHz clock frequency

8-byte data buffer

8-bit host controller interface

Support of

IPMS_RSA Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
Verilog
VHDL

Cryptographic Processor Core for Public Key En¬cryption

processor core for modulo n multiplication and exponentiation (RSA) with high speed and high bit sizes

Data rates (for a 1024 bit system at 25 MHz clock frequency)

1024 bit RSA up to 10 kbit/s

IMMS SENT Transmitter Soft IP
IMMS GmbH
All Geometries
All Processes
PT
Verilog

Silicon-proven Verilog implementation of a flexible configurable SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. Up to 16-bit data from two independent sensors.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 361 to 372 out of 372

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X-FAB will take no responsibility nor any liability whatsoever for the information or products offered or provided by the other IP suppliers at the database of the Intellectual Partner Network. X-FAB shall have no liability towards the customers for any use of and/or reliance of the products provided by the other IP suppliers at the database of the Intellectual Partner Network.

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