IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
IPMS_AES Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Cryptographie core according to AES standard

Features

High processing speed of 100 Mbit / s (128 bit key, 25 MHz).

Same speed for coding and decoding.

Key widths of 128, 192 and 256 bit are implemented

120 kGates.

IPMS_CAN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

CAN-Controller

Features

implementation of the Basic CAN specification

no generated Overload Frames

receiving and transmitting of both identifiers (CAN specification 2.0B)

programmable data rate up to 1 Mbit/s

programmable

IPMS_DES Other
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Cryptographic Processor Core for the DES Algorithm

The hardware realizes a flexible DES core to encrypt and decrypt data with high speed. The encryption /decryption of a 64 bit data set takes 16 clock periods.

IPMS_ECC Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Processor core for Elliptic Curve Cryptography

IEEE-Standard 1076-1993 compliant synthesizable VHDL model for utiliza¬tion as macro cell in ASIC and FPGA designs

Diffie-Hellman key exchange proto¬col exists

Implementation of other proto¬cols based o

IPMS_IIC Other
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

The core realized the I²C-bus protocol

Features:

Master and receive mode realized

Bus node address and data transmission rate are programmable

8 Bit data interface to the controller

All I²C function are implemented

Core is multimasterable   

IPMS_IRHSP Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL

IrDA Hight Speed Protocl Stack

Features:

Complete IrDA protocol stack (IrPHY, Framer, IrLAP, IrLMP, IAS, TinyTP, IrCOMM, IrOBEX)

Primary and secondary function (scalable)

Data rates from 9.6 kbit / s - 16 Mbit / s (scalable)

IR remote control functio

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol

Features

Support of LIN specification 2.0

Programmable data rate between 1 Kbit/s and 20 Kbit/s

4 MHz clock frequency

8-byte data buffer

8-bit host controller interface

Support of

IPMS_RSA Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
Verilog
VHDL

Cryptographic Processor Core for Public Key En¬cryption

processor core for modulo n multiplication and exponentiation (RSA) with high speed and high bit sizes

Data rates (for a 1024 bit system at 25 MHz clock frequency)

1024 bit RSA up to 10 kbit/s

LCVCO2 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO2 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It is based on a cross-coupled bipolar transistor pair. It contains AC-coupled varactors and a special circuit technique for maintaining the D

LCVCO3 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other

LNA1 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA 1 is a low noise amplifier. It shoud be biased by the RF bias cell.

LNA1 LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA1 is a broadband low noise amplifier. It should be bieased by the RF bias cell.

LNA2 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA2 is a low noise amplifier. It should be biased by the RF bias cell

LNA2 LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA2 is a narrowband low noise amplifier. It should be biased by the RF bias cell.

LNA3 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA3 is a low noise amplifier with on-chip inductor. It should be biased by the RF bias cell.

Low Power DDS Other
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

Novel aproach to Direct Digital Synthesis, using a voltage-ladder reference. Accuracy is achieved by using a full resistor ladder array, so bit size equivalent to 12 bits has been shown. Prototypes using an 8 bit system are available on

MIXER Mixer
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_MIXER_CELLS. MIXER is a down conversion mixer based on a Gilbert cell topology. It should be biased by the RF bias cell.

MR74039 Other
Moortec Semiconductor Ltd
0.35 μm
XH035
ID
GDSII
Verilog

The MR74039 is a fully integrated temperature sensor with a 12 Bit digital output designed in the XFab 0.35um XH035 process. It utilises a 12 bit Sigma Delta ADC for increased precision (0.25ºC). The temperature measurement range is fr

OEIC_Fast Optical Receiver Channel
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. OEIC_Fast is a fast DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.

OEIC_Sensitive Optical Receiver Channel
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. OEIC_Sensitive is a sensitive DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.

PA Power Amplifiers
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_PA_CELLS. PA is a non-linear Power Amplifier that is intended for the transmission of ASK and FSK signals. Its output power level can be digitally controlled in 4 steps. It should be biased by the RF bias cell.

PWM Other
Ridgetop Group
0.35 μm
XH035
ID
GDSII

250kHz PWM for DC-DC converters

QCADB5_35X Other
QualCore Logic, Inc.
0.35 μm
XH035
PT
GDSII
Schematic

Connectivity IP. This is a product chip.

QCBGB10_35X Voltage Regulator
Bias
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Bandgap Voltage Reference and Current Bias Cell.

QCBIAS1_35X Current Reference
Bias
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Current Reference and Current Biasing Cell.

QCCMP4_35X Comparators
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Comparator Cell with N-Channel Inputs

QCDAC4_35X DAC
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Resistive String architecture.

QCOP4_35X Operational Amplifier
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Operational Amplifier Cell with P-Channel Inputs

QCOP5_35X Operational Amplifier
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Reference Amplifier

QCPOR4_35X Power on Reset
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Power On Reset cell

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 331 to 360 out of 371

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