IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
LCVCO3 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other

RINGVCO1 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_VCO_CELLS. RINGVCO1 is a fully integrated VCO. It should be biased by the RF bias cell. It consists of a ringoscillator that is tuned by switching the delay chain between 2 and 4 delay stages. The transition between the two borders i

MIXER Mixer
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_MIXER_CELLS. MIXER is a down conversion mixer based on a Gilbert cell topology. It should be biased by the RF bias cell.

PA Power Amplifiers
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_PA_CELLS. PA is a non-linear Power Amplifier that is intended for the transmission of ASK and FSK signals. Its output power level can be digitally controlled in 4 steps. It should be biased by the RF bias cell.

DIV32 Divider
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed divider ratio of 32. It should be biased by the RF bias cell.

OEIC_Fast Optical Receiver Channel
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. OEIC_Fast is a fast DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.

OEIC_Sensitive Optical Receiver Channel
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. OEIC_Sensitive is a sensitive DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.

DPIN Integrated Photodiode
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. DPIN_5050 and DPIN_50100 are fast photodiodes with a vertical PIN structure optimized forred light (660nm).

aopac01 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: A_CELLS. aopac01 is a low power internal frequency-compensated CMOS operational amplifier with pmos input stage

aopac14 Operational Amplifier
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. aopac14 is a high-voltage (VDD up to 10V), low-power, internally-compensated CMOS OpAmp with NMOS input stage.

aopac15 Operational Amplifier
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. aopac15 is a high-voltage, internally-compensated CMOS OpAmp with NMOS input stage and bipolar emitter-follower output. The incorporated level shifters allow the EN and ENB inputs to be controlled by 5V circuitry.

abiac07 Bias
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. abiac07 is a high-voltage bias cell. The circuit forces a current of 2µA (approx.) to flow through pghv PMOS with W/L ratio of 10µm/10µm and nmv NMOS with W/L ratio of 10µm/12µm.

abiac08 Bias
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. abiac08 is a high-voltage bias cell. THe circuit forces a current of 2µA (approx.) to flow through pgmv PMOS with W/L ratio of 10µm/10µm and nhv NMOS with W/L ratio od 10µm/12µm. The cell features low-cost process option and is a co

adrvc01 Driver
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. adrvc01 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output (high-side switch). High input voltage makes the output go low (connected to ground). The rising slope of the output signal c

adrvc02 Driver
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. adrvc02 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output (low-side switch). High input voltage makes the output go low (connected to ground).

adrvc03 Driver
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. adrvc03 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output (high-side switch). High input voltage makes the output go low (connected to ground). The rising slope of the output signal c

aopac01 Operational Amplifier
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS. aopac01 is a general purpose internally compensated CMOS OpAmp with P-MOS input stage and source follower output stage.

aregc02 Voltage Regulator
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. aregc02 is a 12V/3.3V linear voltage regulator for up to 20mA load current. The regulator is powered via its high-voltage input.

adrvc02 Driver
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. adrvc02 is a driver circuit for external loads (relays, LEDs, etc). The circuit features PNOS open-drain output (high-side switch). The layout of adrvc02 makes it easy to incorporate in the flat IO ring.

adrvc03 Driver
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. adrvc03 is a driver circuit for external loads (realys, LEDs, etc). The circuit features NMOS open-drain output (low-side switch). The layout of adrvc03 makes it easy to incorporate in the flat IO ring.

abiac04 Bias
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. abiac04 is a high voltage bias cell. The circuit forces a current of 2µA (approx.) to flow through PHV with W/L ratio of 8µm/12µm and NHV with W/L ratio of 8µm/14µm.

arcoc07 Oscillator
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. arcoc07 is a high-voltage 400kHz current-balancing RC oscillator with internal R and C. The cell features low temperature coefficient of clock frequency, constant duty cycle, and low power consumption.

LNA1 LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA1 is a broadband low noise amplifier. It should be bieased by the RF bias cell.

LNA2 LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA2 is a narrowband low noise amplifier. It should be biased by the RF bias cell.

BIAS Bias
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: BIAS Library: RF_BIAS_CELLS. BIAS is a bias cell intended for use with the various RF building blocks. It is based on a bandgap reference and voltage-to-current converters. Current biasing is preferable because of the higher immunity to interferenc

axtoc02_3v3 Crystal Oscillators
X-FAB
0.18 μm
XC018
PT
Schematic
Layout
Analog Library

XC018 LP 3.3V axtoc02_3v3 is a robust 1-4 MHz crystal oscillator for supply voltage range from 2.4 to 3.6V.

BIAS Bias
X-FAB
0.60 µm
XB06
PT
Verilog
Schematic
Layout
Analog Library

XB06: LNA library: RF_BIAS_CELLS. BIAS is a bias cell intended for use with various RF building blocks. It is designed as a bandgap reference as well as voltage-to-current converter. Current biasing is preferable because of the higher immunity to interfer

IPMS_RSA Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
Verilog
VHDL

Cryptographic Processor Core for Public Key En¬cryption

processor core for modulo n multiplication and exponentiation (RSA) with high speed and high bit sizes

Data rates (for a 1024 bit system at 25 MHz clock frequency)

1024 bit RSA up to 10 kbit/s

EnDAT2.2 Soft IP
MAZeT Gmbh
All Geometries
All Processes
VS
VHDL

Sensor Interface used in positioning systems. Visit MAZet website for datasheet.

SUPI4 Soft IP
MAZeT Gmbh
All Geometries
All Processes
VS
VHDL

Interbus Slave Controller Version 4. Visit MAZeT website for datasheet.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 331 to 360 out of 370

*Disclaimer:
The Intellectual Partner Network is a web database provided by X-FAB in cooperation with selected partners. Both X-FAB and a variety of different IP supplier offer their IP to customers using X-FAB’s foundry process. X-FAB will support customers to get in direct contact with the relevant IP supplier.

X-FAB will take no responsibility nor any liability whatsoever for the information or products offered or provided by the other IP suppliers at the database of the Intellectual Partner Network. X-FAB shall have no liability towards the customers for any use of and/or reliance of the products provided by the other IP suppliers at the database of the Intellectual Partner Network.

X-FAB's own IP is subject to a license agreement. X-FAB IP marked with “*” are part of the Master Kit or Master Kit Plus library. If you can not find the IP you are looking for, please contact the respective sales manager in your region. We continuously extend our libraries and offer a custom cell development service as well.