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Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
aporc03_5v Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 5V aporc03_5v is a Power-on-Reset (POR) circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

aporc01 Power on Reset
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low.

aporc02 Power on Reset
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 aporc02 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on both the rising and failing edge of the supply voltage. During power-on, POR outputs is kept high as long as the supply voltage is below the threshold voltage.

aporc03 Power on Reset
X-FAB
0.60 µm
XT06
Layout
Schematic
Analog Library

XT06 aporc03 is a Power-on-Rest circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept high as long as the supply voltage is below the high threshold.

QCPOR4_35X Power on Reset
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Power On Reset cell

aporc01_3v3 Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aporc01_3v3 is a dynamic power-on-reset circuit (POR). The cell is suitable for applicaitons where low consumption is important.

aporc02_3v3 Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aporc02_3v3 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.

aporc03_3v3 Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aporc03_3v3 is a Power-on-Rest circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

aporc03_5v Power on Reset
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V aporc03_5v is a power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.

CM1412ae Power on Reset
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

2Low consumption Power-On Reset (POR) core. The core has a voltage sense (configurable 0.9V - 5.5V), an internal current bias circuit and two configurable assertion delays (default are > 1μs and > 20μs). A configurable hysteresis (default 100mV).

aporc02_1v8 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aporc02_1v8 is a Power-on-Reset circuit with hysteresis. Both high and low reset signals are available. Reset signals are generated on power-on and power-off transitions. 40mV (typ) hysteresis for safer operation.

aporc03_1v8 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 1.8V aporc03_1v8 is a Power-on-Reset circuit with hysteresis. Both high and low reset signals are available. Reset signals are generated on power-on and power-off transitions. 35mV (typ) hysteresis for safer operation.

aporc02_3v3 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aporc02_3v3 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on power-on and power-off transitions. Both high and low (POR and PORB) reset signals are available.

aporc03_3v3 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aporc02_3v3 is a Power-on-Reset circuit. Reset signal are generated on power-on and power-off transitions. Both high and low (POR and PORB) reset signals are available.

EnDAT2.2 Soft IP
MAZeT Gmbh
All Geometries
All Processes
VS
VHDL

Sensor Interface used in positioning systems. Visit MAZet website for datasheet.

SUPI4 Soft IP
MAZeT Gmbh
All Geometries
All Processes
VS
VHDL

Interbus Slave Controller Version 4. Visit MAZeT website for datasheet.

IPMS_16550 Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

The UART-core IPMS_16550 realize the functionality of an serial interface.

Features:

Data rates, data formats and interrupt events are programmable

compatible to UART 16550

high flexibility in different uses

IPMS_AES Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Cryptographie core according to AES standard

Features

High processing speed of 100 Mbit / s (128 bit key, 25 MHz).

Same speed for coding and decoding.

Key widths of 128, 192 and 256 bit are implemented

120 kGates.

IPMS_CAN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

CAN-Controller

Features

implementation of the Basic CAN specification

no generated Overload Frames

receiving and transmitting of both identifiers (CAN specification 2.0B)

programmable data rate up to 1 Mbit/s

programmable

IPMS_ECC Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL
Verilog

Processor core for Elliptic Curve Cryptography

IEEE-Standard 1076-1993 compliant synthesizable VHDL model for utiliza¬tion as macro cell in ASIC and FPGA designs

Diffie-Hellman key exchange proto¬col exists

Implementation of other proto¬cols based o

IPMS_IRHSP Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
VHDL

IrDA Hight Speed Protocl Stack

Features:

Complete IrDA protocol stack (IrPHY, Framer, IrLAP, IrLMP, IAS, TinyTP, IrCOMM, IrOBEX)

Primary and secondary function (scalable)

Data rates from 9.6 kbit / s - 16 Mbit / s (scalable)

IR remote control functio

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol

Features

Support of LIN specification 2.0

Programmable data rate between 1 Kbit/s and 20 Kbit/s

4 MHz clock frequency

8-byte data buffer

8-bit host controller interface

Support of

IPMS_RSA Soft IP
Fraunhofer IPMS
All Geometries
All Processes
VS
Verilog
VHDL

Cryptographic Processor Core for Public Key En¬cryption

processor core for modulo n multiplication and exponentiation (RSA) with high speed and high bit sizes

Data rates (for a 1024 bit system at 25 MHz clock frequency)

1024 bit RSA up to 10 kbit/s

LCVCO2 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO2 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It is based on a cross-coupled bipolar transistor pair. It contains AC-coupled varactors and a special circuit technique for maintaining the D

LCVCO3 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other

RINGVCO1 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_VCO_CELLS. RINGVCO1 is a fully integrated VCO. It should be biased by the RF bias cell. It consists of a ringoscillator that is tuned by switching the delay chain between 2 and 4 delay stages. The transition between the two borders i

avcoc01_3v3 VCO
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V avcoc01_3v3 is a voltage controlled oscillator (VCO).

aregc01 Voltage Regulator
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aregc01 is a 5V / 3.3V positive voltage linear regulator for up to 10 mA load current.

aregc02 Voltage Regulator
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aregc02 is a 2.4V / 3.3V positive voltage switching regulator for on-chip loads and up to 10 mA load current.

aregc01 Voltage Regulator
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS_HV. For MOS module only. aregc01 is a 5V/3.3V linear voltage regulator for up to 20mA load current. The regulator is powered viz its high voltage input.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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