28 entries, filtered by: Characterization
Published: February 2002

Result of a large-area, low-capacitance lateral p-i-n photodiode in silicon-on-insulator (SOI) are presented. This photodiode possesses an antireflection coating optimized for blue light and is therefore appropriate for scintillation detector applications. An average external quantum efficiency of 78.6% and 68.4% is achieved for λ = 430 nm and 400 nm, respectively.


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Published: April 2002

The adjustment of emitter efficiency by variation of doping profiles or application of lifetime control techniques such as irradiation of electrons and helium are two generally recognized concepts for the improvement of power device characteristics. In this work both concepts were studied by use of device simulation for the development of an IGBT and freewheeling diode chipset for 3.3kV.


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Published: April 2002

We attain a PIN photodiode combining high responsivity, fast response and low capacitance in BiCMOS technology. Only a slight process modification, having no verifiable influence on the transistor parameters is necessary. We achieve bandwidths of 625MHz and 240MHz at 670 and 780nm as well as a quantum efficiency of 96.5%.


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Published: March 2003

Standard high frequency n-p-n poly emitter transistor pairs show a significant parameter offset during the matching characterization depending on the position on the wafer. Special octagon matching transistors on the other hand have a good matching behavior. The main reason for the offset of the high frequency transistors is a dimensional difference in the emitter cut due to an non-uniform development process of the resist mask for the emitter cut etch and / or proximity effects. By the use of a modified photo resist and development process the matching characteristics for all used transistor types could be significantly improved.


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Published: September 2005

During the evolution of RF bipolar transistors, much efforts were spent to optimize the base design. Device engineers came up with concepts like graded dopant profiles, SiGe and SiGe:C base layers, elevated base structures, etc. Regarding the collector, selectively implanted collectors (SIC) were introduced to increase both the cutoff frequency ft and the maximum frequency of oscillation fmax. In this work we focus on the collector-emitter breakdown voltage BVCE0 and its relation to ft for differently designed SICs of Si-based RF bipolar transistors.


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Published: September 2005

This paper presents the results of a three and a half year R&D project for low cost micromachined gyroscopes. As starting point of this work the application requirements of enhanced automotive applications such as Advanced Driving Assistant Systems (ADAS) are given. Based on these demands the sensor development is carried out.


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Published: April 2006

A wafer-level testing method is investigated for an early stage of the manufacturing process applied to accelerometers. The approach consists of performing optical measurement of the modal responses of the MEMS structures, and uses this information in an inverse identification algorithm based on a FE model.


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Published: April 2006

In the paper new testing methods for MEMS will be presented that can be applied on wafer level in early stage of the manufacturing process. First measurements of the eigenfrequencies test specimen were done. A Finite Element model was created to determine the plate thickness for the measured eigenfrequencies. There is a good agreement between the microscopic determined real thicknesses and the calculated thicknesses. Also a stochastic model was created to describe the influence of different parameters on the calculated thickness of membrane.


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Published: March 2007

MEMS, such as surface micromachined inertial sensors, require cap wafer bonding to protect the sensitive structures at the wafer level against mechanical damage and environmental influences, in order to allow the finalization of the wafer processing, dicing and packaging. In most cases, the cap is solely for mechanical protection without any electrical function, because standard wafer bonding processes cannot provide the possibility of local electrical contacts from system to cap wafer (glass frit, adhesive and low temperature direct bonding are nonconductive, while the metal interlayer bonding bond frame is a large, dominating contact area).


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Published: May 2007

A new smart power SOC IC process including up to 50V HV-MOS transistors, SONOS principle based non-volatile memory components and analog devices using an advanced 0.18μm platform is presented. Process architecture and device portfolio are focused on automotive applications e.g. sensor signal conditioning and integrated output drivers. HV-MOS and SONOS integration as well as device properties are discussed with regard to reliability aspects. Additionally key features of NPN bipolar transistors and depletion NMOST are given.


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