150 entries
Published: September 2011

For the Synchronous DC-DC converter switching performance of low-voltage power MOSFETs, the gate-drain charge density (Qgd) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (Ron.sp) and Qgd is commonly used to quantify the switching performance for a specified off-state breakdown voltage (BVds).


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Published: September 2011

Wire Bond Shear (WBS) test is a method for evaluating the strength of a ball bond, to complement wire pull test. In foundry, wafer-level (WLR) WBS provides a quick way to demonstrate the integrity of metal bond pad, backend scheme as well as bond or via design. This is a big challenge for WLR WBS outsourcing as many of the factors affecting shear strength lying on the wire bonding parameters and shear test setup. This paper presents the outsourcing experiences of WBS tests and good shear strength was achieved from the outsource laboratory.


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Published: September 2011

A study on the effect of process fabrication for MIM capacitors analog matching performance was carried out, impacts from the MIM dielectrics, capacitor top and bottom metal materials, capacitor metal etch, wet cleaning, annealing process will be revealed by comparing the Pelgrom coefficients, i.e. the dependence of difference in capacitance of the matching pairs with respect to their corresponding square root of capacitor areas, the smaller the difference the better the matching.


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Published: September 2011

Diodes inherent in a CMOS process are light sensitive and could be exploited as photodetectors. To detect light the photo generated carriers need to be separated by the electrical field of an internal pn junction. They are either generated inside the depletion region or can get there by diffusion. The depth where these carriers are generated depends strongly on the wavelength. The generation profile, the pn junction depth and the diffusion length all impact the spectral sensitivity.


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Published: September 2011

This paper presents a simple but effective way to improve an NMOS transistor’s ESD robustness for use in I/O pads. Simulation and physical failure analysis has been performed to identify the source of the ESD failure. Process splits have been performed primarily at LDD (Lightly Doped Drain) implant and salicidation process based on data presented in this paper.


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Published: September 2011

Using a trench isolated 650V quasi-vertical n-channel DMOS as a starting point several new 650V transistor types have been evaluated. Mainly by design measures a 650V depletion DMOS, a 650V PMOS and a 650V IGBT were created for a modular integration into the process flow.


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Published: September 2011

IC content in cars has been growing exponentially, adding significant complexity to automotive chip design and manufacturing. Today’s cars feature many semiconductor applications such as tire pressure monitoring sensors and accelerometers for airbag systems. Add electronic components to improve engine performance, increase fuel efficiency, control modern entertainment and communications devices, provide Internet capability and handle new comfort functions... Now add the challenge of making the associated ICs survive for many years in extreme heat and cold, rain and snow, salt, g-forces, humidity, dry and dusty conditions...and you’ve got your hands full designing for one of the most harsh IC operating environments. 


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Published: July 2011

In low leakage MOS device fabrication, careful pn junction design is critical to control overall device leakage, such as Band-To-Band Tunneling (BTBT) and Gate-Induced Drain Leakage (GIDL) that are always taken into consideration by device designers. Source/Drain implantation also play a very important role in suppressing silicon dislocation effect, which increases implanted species transient-enhanced diffusion (TED) and induces shallow-junction leakage.


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Published: July 2011

An enhancement-mode Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) device has been developed in 0.13μm technology platform. The single-transistor (1-T) SONOS device in NOR Flash memory array utilizes n-channel cells. The development of 1-T SONOS is not an easy feat due to many disturbs experienced by the cells during operation.


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Published: July 2011

Are you looking for a highly reliable embedded non-volatile memory (NVM) solution in an advanced technology node that is easy to integrate into your design? One that can serve as a platform for developing complete product families? This free webinar introduces X-FAB’s new XH018 eFlash option – the industry’s most cost-effective combination of high voltage and embedded flash for complex SoCs. Find out how it works and why eFlash is ideally suited for for high-speed microcontroller, digital power and automotive applications.


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