87 entries, filtered by: CMOS
Published: November 2008

Wafer Level Reliability Gate Oxide Integrity tests such as voltage-ramped and constant current stress have been conducted on area plate-type, poly edge and STI edge intensive test structures. The WLR tests are required for qualifying the process of integrating 3.3 nm and 12.5 nm dual gate oxide operated under the bias of 1.8V and 5V respectively on a single chip.


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Published: November 2008

Several methods have been investigated for gettering impurities during CMOS processing, in order to achieve high-quality oxides on thick SOI. The use of buried implants, buried polysilicon, surface implants, and isolation trenches was found to significantly improve the oxide quality in each case


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Published: August 2008

The XC018 series is X-FAB’s 0.18 micron Modular Logic and Mixed Signal Technology. The platfrom is ideal for SOC application. Main target applications are standard cell, semi-custom and full custom designs for Automotive, Consumer, Industrial as well as Telecommunication products, while the low power and high voltage process is ideal for mobile applications as well as display drivers or controllers. Based upon the industrial standard single poly with up to six metal layers 0.18-micron drawn gate length N-well process, modules are also available for metal-insulatormetal capacitors, high resistive poly, dual gate oxide (1.8V with 3.3V or 5.0V) transistors.


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Published: July 2008

With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters.


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Published: July 2008

Hot carriers, the high kinetic energy carriers due to high electric field in the channel region, are injected into the gate oxide and form interface states, which in turns causes degradation of MOS device performance. The hot carrier effect has become more severe as the device size continues to scale down to submicron range. This aging phenomenon that threatens the circuit and product lifetimes warrants it to be considered as the key challenge in reliability.


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Published: July 2008

The XC10 Series is X-FAB‘s One-Micron Modular Mixed Signal Technology. Main target applications are standard cell, semi-custom and full custom designs for Automotive, Consumer, Industrial and Telecommunication products. The process enables mixed-signal systems on one chip by its nonvolatile memory and sensor integration capabilities.
Based on a state of the art very cost effective single poly single metal 1.0-micron minimum feature size N-well process for mixed-signal and high voltage applications, various process modules are available for high performance analog and high voltage circuits. Using the non-volatile memory modules integration of EEPROM, OTP or NV latches is possible.
Technology variants for integrated MEMS are available.


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Published: July 2008

In this work an attempt is made to extract Dual Pearson moments from 1-D Monte Carlo simulated profiles, and these moments are used for 2-D simulations. This approach gives same accurate implant profile as Monte Carlo, but simulation time is significantly reduced.


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Published: July 2008

Experimental condition of thin SAB Oxide around 350Å coupling with 400Å Contact SiON film has exhibited the worst data retention behavior in One Time Programmable (OTP) & Multiple Time Programmable (MTP) memory device.


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Published: July 2008

In 0.11um and larger technology node non-volatile memory process integration, undesired cobalt salicide residue formation is found to degrade ohmic contact resistant and cause severe yield loss. TiN/Ti/Co stack is applied in the process to get good CoSi2 formation. The abnormal salicide residue formation is detected after cobalt stripping process which is applying a two step selective wet etching.


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Published: July 2008

Rapid increasing demand towards high voltage MOSFETs device integrated in low voltage CMOS analog and digital circuits for automobile and power management application has driven the development of 0.18um high voltage lateral diffused MOSFET (LDMOS) which capable to have 80V breakdown voltage. During designing this high voltage LDMOS, it is observed that the device performance is very dependent towards the device geometry particularly poly overlap length on STI. Thus, in this paper, the effects of poly overlap length on STI plate for high voltage LDNMOS have been studied extensively during the off-state condition.


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