90 entries, filtered by: CMOS
Published: November 2008

The fast scanning mechanism of High Current batch Implanter is achieved by spinning the wafer disk with angular speed more than 1200 Rotation-Per-Minute (RPM). If particles hit device wafers during implant it can cause serious damage to device structure. Particle generation areas are mainly from Source terminal, Accelerator Column, Plasma Flood Gun (PFG) and beam line wall.


More
Published: November 2008

The work presented here show the impact of different reticle transmission ratio (macro pattern density) to metal profile and CD bias of metal etch process. These impacts are due to macro loading and passivation effects differ when pattern density at wafer level changed. We also try to investigate the impact of passivation gas to above phenomenon.


More
Published: November 2008

The work presented here shows a change in migration behaviour of a transferred AlCu metallization system. Different failure mechanisms in metallization are known. Migration effects like electro-, thermo- and stress migration are the main failure mechanisms in a metallization. This study shows the detection and exploration of a significant change in the migration mechanism of a wide lines of a top level interconnect of a standard metallization. The study demonstrates the differences of the transferred metallization system and the influence for the degradation behaviour and reliability.


More
Published: November 2008

Wafer Level Reliability Gate Oxide Integrity tests such as voltage-ramped and constant current stress have been conducted on area plate-type, poly edge and STI edge intensive test structures. The WLR tests are required for qualifying the process of integrating 3.3 nm and 12.5 nm dual gate oxide operated under the bias of 1.8V and 5V respectively on a single chip.


More
Published: November 2008

Several methods have been investigated for gettering impurities during CMOS processing, in order to achieve high-quality oxides on thick SOI. The use of buried implants, buried polysilicon, surface implants, and isolation trenches was found to significantly improve the oxide quality in each case


More
Published: August 2008

The XC018 series is X-FAB’s 0.18 micron Modular Logic and Mixed Signal Technology. The platfrom is ideal for SOC application. Main target applications are standard cell, semi-custom and full custom designs for Automotive, Consumer, Industrial as well as Telecommunication products, while the low power and high voltage process is ideal for mobile applications as well as display drivers or controllers. Based upon the industrial standard single poly with up to six metal layers 0.18-micron drawn gate length N-well process, modules are also available for metal-insulatormetal capacitors, high resistive poly, dual gate oxide (1.8V with 3.3V or 5.0V) transistors.


More
Published: July 2008

With the further scaling down of CMOS devices, hot carrier induced degradation has become one of the most important reliability concerns. In the hot carrier effect, carriers are accelerated by the channel electric fields and become trapped in the oxide. These trapped charges cause time dependent shifts in measured device parameters.


More
Published: July 2008

Hot carriers, the high kinetic energy carriers due to high electric field in the channel region, are injected into the gate oxide and form interface states, which in turns causes degradation of MOS device performance. The hot carrier effect has become more severe as the device size continues to scale down to submicron range. This aging phenomenon that threatens the circuit and product lifetimes warrants it to be considered as the key challenge in reliability.


More
Published: July 2008

The XC10 Series is X-FAB‘s One-Micron Modular Mixed Signal Technology. Main target applications are standard cell, semi-custom and full custom designs for Automotive, Consumer, Industrial and Telecommunication products. The process enables mixed-signal systems on one chip by its nonvolatile memory and sensor integration capabilities.
Based on a state of the art very cost effective single poly single metal 1.0-micron minimum feature size N-well process for mixed-signal and high voltage applications, various process modules are available for high performance analog and high voltage circuits. Using the non-volatile memory modules integration of EEPROM, OTP or NV latches is possible.
Technology variants for integrated MEMS are available.


More
Published: July 2008

In this work an attempt is made to extract Dual Pearson moments from 1-D Monte Carlo simulated profiles, and these moments are used for 2-D simulations. This approach gives same accurate implant profile as Monte Carlo, but simulation time is significantly reduced.


More