87 entries, filtered by: CMOS
Published: August 2009

Resistance of contacts on nonsalicided active must be sufficiently low in order for a device to function. The objective of the work presented here is to discuss steps taken to reduce initially high contact resistance on non-salicided active of a high breakdown voltage transistor to meet functional requirement. In order to create a special 30V high voltage transistor in a NAND flash device, the active region between gate and junction has to be non-salicided. Therefore, the contact resistance needs to be lowered down by other means. This paper shows substantially reduction in contact resistance value and better resistance distribution uniformity across a wafer through a combination of plug implant and improved contact etching with O2 flush condition and additional oxide etching.


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Published: August 2009

This study was carried out to investigate the bimodal distribution of Vt (threshold voltage) of 3.3V differential pair PMOS structure within a wafer in which the abnormal transistor shows half lower than normal threshold voltage value and higher off state leakage current. The root cause was identified by simulation which is increasing gate oxide thickness of thin gate oxide area and finally matches behavior of the abnormal transistor with low threshold voltage and high off state leakage. The solution was implemented with O2 descum process into the dual gate oxide process flow, which O2 descum process was inserted after photo resist patterning for thick gate oxide in order to remove potential thin photo resist scum which is blocking wet etch reaction to oxide and causes thick gate oxide to remain at the thin gate oxide area. Details evaluation, measurement and result will be further discussed.


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Published: August 2009

In SOC (System on Chip) technology, the various types of devices located on an IC chip typically have different operating voltages thus requiring multiple gate oxide layers of different thickness to be formed. In order to form different gate oxide, several oxide removal and growth steps have to be carried out which make the process more complex and particularly have a detrimental impact on the Shallow Trench Isolation (STI) structures.


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Published: August 2009

Monolithically integrated photodiodes with high spectral responsivity over the entire visible and the near infrared spectral range are of growing interest for the semiconductor industry, since the next generation of optical data storage devices (Blue DVD) will soon be brought to market. In this paper, the bandwidth of photodiode dependence on the junction implant conditions and thermal budget was simulated by TCAD. It shows significant dependence on these process conditions. The corresponding mechanism related to RC delay, relationship between depletion region and light absorption will be discussed in detail with the help of simulation pictures and simple model explanation.


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Published: July 2009

This paper presents an investigation of low oxide breakdown voltage on polysilicon-oxide-diffusion (POD) capacitor. The dielectric was 7 nm thermal oxide which was grown simultaneously for MOS transistor as gate oxide. The V-Ramp measurement showed bimodal distribution of Vbd with one circular patch having < 7 V instead of the target Vbd (10 V). The size of the patch depends on the POD capacitor area. This behavior was not observed on gate oxide of MOS transistor and 22.5 nm POD capacitor. Process partition check, including wafer orientation and wafer slot arrangement was conducted. The specific process step causing the patch signature has been identified successfully.


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Published: June 2009

A combination of conventional cross sectional process and device simulations combined with top down and 3D device simulations have been used to design and optimise the integration of a 100V Lateral DMOS (LDMOS) device for high side bridge applications. This combined simulation approach can streamline the device design process and gain important information about end effects which are lost from 2D cross sectional simulations. Design solutions to negate detrimental end effects are proposed and optimised by top down and 3D simulations and subsequently proven on tested silicon.


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Published: November 2008

The work presented here shows a series of engineering runs to improve the AC HCI lifetime for a 0.60μm NMOS. The conventional method of increasing NLDD energy and reducing NLDD dose did not achieve significant improvement. The study concludes that tilting the NLDD implant, coupled with prolonging the NLDD anneal and increasing the Poly CD can improve the lifetime significantly. A short HCI test was performed to compare the response of different splits.


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Published: November 2008

The fast scanning mechanism of High Current batch Implanter is achieved by spinning the wafer disk with angular speed more than 1200 Rotation-Per-Minute (RPM). If particles hit device wafers during implant it can cause serious damage to device structure. Particle generation areas are mainly from Source terminal, Accelerator Column, Plasma Flood Gun (PFG) and beam line wall.


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Published: November 2008

The work presented here show the impact of different reticle transmission ratio (macro pattern density) to metal profile and CD bias of metal etch process. These impacts are due to macro loading and passivation effects differ when pattern density at wafer level changed. We also try to investigate the impact of passivation gas to above phenomenon.


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Published: November 2008

The work presented here shows a change in migration behaviour of a transferred AlCu metallization system. Different failure mechanisms in metallization are known. Migration effects like electro-, thermo- and stress migration are the main failure mechanisms in a metallization. This study shows the detection and exploration of a significant change in the migration mechanism of a wide lines of a top level interconnect of a standard metallization. The study demonstrates the differences of the transferred metallization system and the influence for the degradation behaviour and reliability.


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