87 entries, filtered by: CMOS
Published: November 2010

This paper suggests an improved method to round off the concave corners of the deep trenches formed by plasma etch. The corner rounding technique, sacrificial oxidation (SACOX) before gate oxidation, has been practiced on the shallow trench isolation (STI) to improve the CMOS leakage performance.


More
Published: October 2010

In the past five years we have seen a huge step in the evolution of MEMS applications. Some may even call it a revolution. Traditionally, Inkjet printer heads and automotive applications have dominated MEMS volume production. Today, demand for MEMS is particularly high in the consumer and mobile sector with further applications appearing every day. Part of this MEMS revolution has been the changing requirements for associated ASIC CMOS intelligence. Many manufacturers who currently use discrete MEMS devices are now seeing the benefits of integrated CMOS.


More
Published: July 2010

Emerging applications in the field of lithium-ion battery management and Power over Ethernet require operating voltages of up to 100V, robust primitive devices and low on-resistance. X-FAB’s enhanced 0.35 micrometer high-voltage foundry process XH035 offers these features combined with high reliability and a small silicon footprint.


More
Published: April 2010

The integration of full custom analog circuitry into a silicon chip, to provide cost-effective products, requires a full understanding of the process architecture and uses completely different methods compared with those used for digital designs. This webinar briefly covers the digital design arena before entering into in-depth discussion of analog layout techniques. It explores the integration of X-FAB-supported primitive devices into complex integrated chips in detail, including diffusions, wells and associated layers that can be merged. The session also covers derivation of "well" combinations from the design layers, and gives guidelines for high-voltage interconnects across these well regions to avoid parasitic leakage paths.


More
Published: April 2010

The high voltage device can be embedded into conventional shallow trench isolation (STI) logic process. Basically, SVX (Smart Voltage Extension) technique was applied in order to integrate 32V high voltage LDMOS into a standard 0.18 micron low voltage CMOS technology without any process change. However, a double hump issue was being observed in high voltage LDNMOS. The double hump phenomenon is mainly occurs due to lower threshold voltage of transistor corner that will lead to high sub-threshold leakage. This paper presents a solution by applying boron implant in HV LDNMOS to suppress the double hump issue. The retrograde baseline CMOS p-well implant is used for this purpose to avoid an additional mask and process step.


More
Published: March 2010

For the first time, this paper demonstrates the experimental results for two types of test structures of field transistors up to 200°C. The field transistor structures which are stripe (conventional) and square ring (new) structures were measured and investigated in term of field leakage current and onstate characterization at high temperature.


More
Published: March 2010

Sub-wavelength structures in metal films have interesting optical properties that can be implemented for sensing applications: gratings act as wire grid polarizer, hole arrays with enhanced transmission can be used as spectral filters. This paper demonstrates the feasibility of these nanostructures using 180 nm and 90 nm complementary metal-oxide semiconductor (CMOS) processes. The metal layers of the process can be used for optical nanostructures with feature sizes down to 100 nm.


More
Published: January 2010

Get an overview of the optical functions and features available as part of X-FABs More-than-Moore technology offering, including the impacts on spectral sensitivity, signal bandwidth, and noise margins. Explore what you need to consider when starting to design your optical product.


More
Published: October 2009

At high temperature, designers are faced with additional technological and design challenges. These issues and how to address them are discussed in this presentation. The webinar looks at X-FAB's high temperature solutions, in particular its latest High Temperature Modular CMOS process (XA035), a comprehensive CMOS offering with High Voltage (HV), RF, and EEPROM integration that is suitable for temperatures up to 175C. The presentation also covers high temperature modelling, application specific reliability and design for reliability.


More
Published: August 2009

OLED-on-CMOS micro-displays are widely studied in the recent years due to the fast development of OLED. However, there are some challenges to fabricate the electrodes of OLED. In this study, the process challenges are discussed, and the surface roughness is suggested to be one of the critical parameters.


More