34 entries, filtered by: Analog
Published: March 2009

The analog foundry business is not just a fad. Many logic foundries are seriously trying to move into this space. However, their transformation requires a change from being contract manufacturers that provide capacity and compete on the cost side to becoming a true provider of feature-rich process technologies with modular front and back ends and comprehensive process characterization. Also, they must offer a complete analog design ecosystem including libraries, analog IP and lots of design support – complicated by the absence of standards. Such capabilities would enable customers to reuse their analog IP across different applications and various technology platforms. This article explores barriers to such a transformation near-term.


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Published: January 2009

The XB06 Series is X-FAB‘s 0.6 Micron BiCMOS Technology. Main target applications are RF circuits and high precision analog applications mixed with digital parts for Telecommunication, Consumer, Automotive and Industrial products. The digital part is fully compatible with X-CMOS 0.6 process family.


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Published: November 2008

The work presented here shows a series of engineering runs to improve the AC HCI lifetime for a 0.60μm NMOS. The conventional method of increasing NLDD energy and reducing NLDD dose did not achieve significant improvement. The study concludes that tilting the NLDD implant, coupled with prolonging the NLDD anneal and increasing the Poly CD can improve the lifetime significantly. A short HCI test was performed to compare the response of different splits.


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Published: November 2008

Wafer Level Reliability Gate Oxide Integrity tests such as voltage-ramped and constant current stress have been conducted on area plate-type, poly edge and STI edge intensive test structures. The WLR tests are required for qualifying the process of integrating 3.3 nm and 12.5 nm dual gate oxide operated under the bias of 1.8V and 5V respectively on a single chip.


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Published: July 2008

The XC10 Series is X-FAB‘s One-Micron Modular Mixed Signal Technology. Main target applications are standard cell, semi-custom and full custom designs for Automotive, Consumer, Industrial and Telecommunication products. The process enables mixed-signal systems on one chip by its nonvolatile memory and sensor integration capabilities.
Based on a state of the art very cost effective single poly single metal 1.0-micron minimum feature size N-well process for mixed-signal and high voltage applications, various process modules are available for high performance analog and high voltage circuits. Using the non-volatile memory modules integration of EEPROM, OTP or NV latches is possible.
Technology variants for integrated MEMS are available.


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Published: July 2008

In this work an attempt is made to extract Dual Pearson moments from 1-D Monte Carlo simulated profiles, and these moments are used for 2-D simulations. This approach gives same accurate implant profile as Monte Carlo, but simulation time is significantly reduced.


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Published: July 2008

The XC06 Series completes X-FAB‘s 0.6 Micron Modular Mixed Signal Technology with embedded Non Volatile Memory and High Voltage options. EEPROM blocks up to 32 kbit as well as Flash memories up to 512 kbit can be integrated in standard cell, semi-custom and full custom designs for Industrial, Automotive and Telecommunication products.
MOS as well as Bipolar Transistors are available with Breakdown Voltages up to 100V. The 5 V CMOS core is compatible in Design Rules and Transistor Performance with state of the art 0.6 μm CMOS Processes.
For analog applications several capacitor and resistor devices are realized, using the Double-Poly-Non-Volatile-Memory architecture.


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Published: May 2007

A new smart power SOC IC process including up to 50V HV-MOS transistors, SONOS principle based non-volatile memory components and analog devices using an advanced 0.18μm platform is presented. Process architecture and device portfolio are focused on automotive applications e.g. sensor signal conditioning and integrated output drivers. HV-MOS and SONOS integration as well as device properties are discussed with regard to reliability aspects. Additionally key features of NPN bipolar transistors and depletion NMOST are given.


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Published: June 2006

High voltage mos transistors usually have a drift zone in the drain region. The conductivity of this drift zone is strongly dependent on the flowing current and gate voltage. Thus it has generally to be modelled with a variable resistance representing the effects on the current. The goal of this work is to show a phenomenological macro model including AC modelling. The model is restricted to a lumped element sub-circuit, which can be processed by a standard spice simulator.


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Published: June 2006

An original work in developing technology that allows the integration of multiple vertical power devices within Power ICs has been presented in this manuscript. The developed technology uses a combination of top and back trenches as well as wafer sawing to achieve complete dielectric isolation between the silicon islands. Each silicon island is capable of holding either single vertical power device or CMOS circuitry. The test structures have been manufactured, wafer diced and individual chips packaged and tested initially for mechanical and thermal stability.


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