EnDAT2.2 Soft IP MAZeT Gmbh All Geometries All Processes VS VHDL Sensor Interface used in positioning systems. Visit MAZet website for datasheet.
SUPI4 Soft IP MAZeT Gmbh All Geometries All Processes VS VHDL Interbus Slave Controller Version 4. Visit MAZeT website for datasheet.
IPMS_430 Microprocessor Fraunhofer IPMS All Geometries All Processes PT VHDL 16 Bit Microcontroller
The core IPMS_430 is compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features are
- 16 bit Risc CPU
- 7 address modes for source operands
- 4 a
IPMS_16CXX Microprocessor Fraunhofer IPMS All Geometries All Processes PT VHDL 8 Bit Microprocessor.
The core IPMS_16CXX realizes a to the PIC 16CXX-family of the firm Microchip compatible 8-bit microcontroller Important features are:
- 8-bit arithmetic (addition, subtraction, logical operations, bit manipulation)
- to 64 k i
IPMS_16550 Soft IP Fraunhofer IPMS All Geometries All Processes PT VHDL The UART-core IPMS_16550 realize the functionality of an serial interface.
Features:
Data rates, data formats and interrupt events are programmable
compatible to UART 16550
high flexibility in different uses
IPMS_AES Soft IP Fraunhofer IPMS All Geometries All Processes VS VHDL Cryptographie core according to AES standard
Features
High processing speed of 100 Mbit / s (128 bit key, 25 MHz).
Same speed for coding and decoding.
Key widths of 128, 192 and 256 bit are implemented
120 kGates.
IPMS_CAN Soft IP Fraunhofer IPMS All Geometries All Processes PT VHDL CAN-Controller
Features
implementation of the Basic CAN specification
no generated Overload Frames
receiving and transmitting of both identifiers (CAN specification 2.0B)
programmable data rate up to 1 Mbit/s
programmable
IPMS_DES Other Fraunhofer IPMS All Geometries All Processes VS VHDL Cryptographic Processor Core for the DES Algorithm
The hardware realizes a flexible DES core to encrypt and decrypt data with high speed. The encryption /decryption of a 64 bit data set takes 16 clock periods.
IPMS_ECC Soft IP Fraunhofer IPMS All Geometries All Processes VS VHDL Processor core for Elliptic Curve Cryptography
IEEE-Standard 1076-1993 compliant synthesizable VHDL model for utiliza¬tion as macro cell in ASIC and FPGA designs
Diffie-Hellman key exchange proto¬col exists
Implementation of other proto¬cols based o
IPMS_IIC Other Fraunhofer IPMS All Geometries All Processes PT VHDL The core realized the I²C-bus protocol
Features:
Master and receive mode realized
Bus node address and data transmission rate are programmable
8 Bit data interface to the controller
All I²C function are implemented
Core is multimasterable
IPMS_IRHSP Soft IP Fraunhofer IPMS All Geometries All Processes VS VHDL IrDA Hight Speed Protocl Stack
Features:
Complete IrDA protocol stack (IrPHY, Framer, IrLAP, IrLMP, IAS, TinyTP, IrCOMM, IrOBEX)
Primary and secondary function (scalable)
Data rates from 9.6 kbit / s - 16 Mbit / s (scalable)
IR remote control functio
IPMS_LIN Soft IP Fraunhofer IPMS All Geometries All Processes PT VHDL LIN (Local Interconnect Network) is a serial communication protocol
Features
Support of LIN specification 2.0
Programmable data rate between 1 Kbit/s and 20 Kbit/s
4 MHz clock frequency
8-byte data buffer
8-bit host controller interface
Support of
BIAS * Bias X-FAB 0.60 µm XB06 PT Verilog XB06: LNA library: RF_BIAS_CELLS. BIAS is a bias cell intended for use with various RF building blocks. It is designed as a bandgap reference as well as voltage-to-current converter. Current biasing is preferable because of the higher immunity to interfer
IPMS_RSA Soft IP Fraunhofer IPMS All Geometries All Processes VS Verilog Cryptographic Processor Core for Public Key En¬cryption
processor core for modulo n multiplication and exponentiation (RSA) with high speed and high bit sizes
Data rates (for a 1024 bit system at 25 MHz clock frequency)
1024 bit RSA up to 10 kbit/s
IMMSD2026A Soft IP IMMS GmbH All Geometries All Processes PT Verilog The soft IP module D2026A implements a SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. The SENT protocol constitutes a low-cost alternative to the LIN and CAN commu
DPIN * Integrated Photodiode X-FAB 0.60 µm XB06 PT Schematic XB06: OEIC Building Block Library. DPIN_5050 and DPIN_50100 are fast photodiodes with a vertical PIN structure optimized forred light (660nm).
aopac01 * Operational Amplifier X-FAB 0.60 µm XB06 PT Schematic XB06: A_CELLS. aopac01 is a low power internal frequency-compensated CMOS operational amplifier with pmos input stage
LNA2 * LNA X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LNA_CELLS. LNA2 is a low noise amplifier. It should be biased by the RF bias cell
dac8 * DAC X-FAB 0.80 µm CX08 PT Schematic CX08A: Analog library. DAC8 is a 8-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recommen
dac10 * DAC X-FAB 0.80 µm CX08 PT Schematic CX08A: Analog library. DAC10 is a 10-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recomm
LNA1 * LNA X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LNA_CELLS. LNA 1 is a low noise amplifier. It shoud be biased by the RF bias cell.
LNA3 * LNA X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LNA_CELLS. LNA3 is a low noise amplifier with on-chip inductor. It should be biased by the RF bias cell.
LCVCO2 * VCO X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LCVCO_CELLS. LCVCO2 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It is based on a cross-coupled bipolar transistor pair. It contains AC-coupled varactors and a special circuit technique for maintaining the D
LCVCO3 * VCO X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other
RINGVCO1 * VCO X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_VCO_CELLS. RINGVCO1 is a fully integrated VCO. It should be biased by the RF bias cell. It consists of a ringoscillator that is tuned by switching the delay chain between 2 and 4 delay stages. The transition between the two borders i
MIXER * Mixer X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_MIXER_CELLS. MIXER is a down conversion mixer based on a Gilbert cell topology. It should be biased by the RF bias cell.
PA * Power Amplifiers X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_PA_CELLS. PA is a non-linear Power Amplifier that is intended for the transmission of ASK and FSK signals. Its output power level can be digitally controlled in 4 steps. It should be biased by the RF bias cell.
DIV32 * Divider X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed divider ratio of 32. It should be biased by the RF bias cell.
OEIC_Fast * Optical Receiver Channel X-FAB 0.60 µm XB06 PT Schematic XB06: OEIC Building Block Library. OEIC_Fast is a fast DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.
OEIC_Sensitive * Optical Receiver Channel X-FAB 0.60 µm XB06 PT Schematic XB06: OEIC Building Block Library. OEIC_Sensitive is a sensitive DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.
