34 entries, filtered by: Reliability
Published: December 2007

Ultra low leakage is considered as a major requirement for most of the common device performance. Larger circuit design size, device threshold voltage scaling, and device dimension shrinkage are causing this dramatically increase in leakage current. This significant increment of leakage with each technology generation warrants that it to be considered as the key challenge in IC design.


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Published: April 2006

In the paper new testing methods for MEMS will be presented that can be applied on wafer level in early stage of the manufacturing process. First measurements of the eigenfrequencies test specimen were done. A Finite Element model was created to determine the plate thickness for the measured eigenfrequencies. There is a good agreement between the microscopic determined real thicknesses and the calculated thicknesses. Also a stochastic model was created to describe the influence of different parameters on the calculated thickness of membrane.


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Published: March 2006

The feasibility of EEPROM memories in SOI process technologies has been proven. It has also been shown that known data retention problems at high temperatures caused by leakage currents can be solved without extra circuitry. In this paper results of EEPROM cell matrix measurements regarding functionality and reliability will be presented. Different cell designs will be compared. Furthermore, a 32x16 bit EEPROM prototype and memory test results will be shown.


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Published: October 2005

In this paper a non-destructive test structure for monitoring the strength of anodic bonded glass silicon wafer compounds is introduced. The realisation of the structure, the calculation of the surface energy using FEM and practical results are shown.


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