33 entries, filtered by: Analog
Published: March 2011

A study has been carried out to improve metal-insulator-metal (MIM) capacitor's capacitance density and linearity performance. The scopes of the study included single MiM and stack MIM structures. Different dielectric schemes were evaluated with their corresponding capacitance density, breakdown voltages and linearity coefficient to voltage and temperature variation etc. characterised.


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Published: February 2011

The CX08 Series is X-FAB‘s 0.8 Micron Modular Mixed Signal Technology. Main target applications are standard cell, semi-custom and full custom designs for Industrial, Telecommunication and Automotive products - including the 42V board net.
Based on a state of the art single poly double metal 0.8-micron drawn gate length N-well process for digital application, various process modules are available for high performance analogue and high voltage circuits.


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Published: December 2010

The CX06 Series is X-FAB‘s 0.6 Micron Modular Mixed Signal Technology. Main target applications are standard cell, semi-custom and full custom designs for Industrial, Automotive and Telecommunication products.
Based on a state of the art single poly double metal 0.6-micron drawn gate length N-well process for digital application, process modules are available for triple metal and double poly high performance analogue circuits.


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Published: August 2010

The XHB06 is X-FAB's 0.6 Micron High-Voltage Bipolar CMOS DMOS (BCD) Technology, optimized for applications requiring operating voltages of 5V to 30V. Main target applications are power management, RF circuits and high precision analog applications mixed with digital parts for Telecommunication, Consumer, Automotive and Industrial products. The digital part is fully compatible with X-CMOS 0.6 process family.


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Published: July 2010

A novel 0.18μm 200V integrated technology based on Partial SOI and lateral Super Junctions devices is presented. The dielectric isolation inherent in SOI allows simple and areaefficient integration of electrically floating CMOS and HV devices while removing all substrate carrier injection-related parasitic effects. The Super Junctions give a competitively low on-resistance of HVMOS and provide a wide-range breakdown voltage-scaling capability.


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Published: April 2010

The integration of full custom analog circuitry into a silicon chip, to provide cost-effective products, requires a full understanding of the process architecture and uses completely different methods compared with those used for digital designs. This webinar briefly covers the digital design arena before entering into in-depth discussion of analog layout techniques. It explores the integration of X-FAB-supported primitive devices into complex integrated chips in detail, including diffusions, wells and associated layers that can be merged. The session also covers derivation of "well" combinations from the design layers, and gives guidelines for high-voltage interconnects across these well regions to avoid parasitic leakage paths.


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Published: April 2010

The high voltage device can be embedded into conventional shallow trench isolation (STI) logic process. Basically, SVX (Smart Voltage Extension) technique was applied in order to integrate 32V high voltage LDMOS into a standard 0.18 micron low voltage CMOS technology without any process change. However, a double hump issue was being observed in high voltage LDNMOS. The double hump phenomenon is mainly occurs due to lower threshold voltage of transistor corner that will lead to high sub-threshold leakage. This paper presents a solution by applying boron implant in HV LDNMOS to suppress the double hump issue. The retrograde baseline CMOS p-well implant is used for this purpose to avoid an additional mask and process step.


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Published: April 2010

An experiment in base and pedestal collector implant has been conducted to study the impact and further improve the performance of a 0.6 micron silicon poly emitter bipolar transistor. It has been shown the bandwidth can be improved form 13GHz to 15GHz with acceptable changes to the other bipolar performances.


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Published: August 2009

Resistance of contacts on nonsalicided active must be sufficiently low in order for a device to function. The objective of the work presented here is to discuss steps taken to reduce initially high contact resistance on non-salicided active of a high breakdown voltage transistor to meet functional requirement. In order to create a special 30V high voltage transistor in a NAND flash device, the active region between gate and junction has to be non-salicided. Therefore, the contact resistance needs to be lowered down by other means. This paper shows substantially reduction in contact resistance value and better resistance distribution uniformity across a wafer through a combination of plug implant and improved contact etching with O2 flush condition and additional oxide etching.


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Published: March 2009

The analog foundry business is not just a fad. Many logic foundries are seriously trying to move into this space. However, their transformation requires a change from being contract manufacturers that provide capacity and compete on the cost side to becoming a true provider of feature-rich process technologies with modular front and back ends and comprehensive process characterization. Also, they must offer a complete analog design ecosystem including libraries, analog IP and lots of design support – complicated by the absence of standards. Such capabilities would enable customers to reuse their analog IP across different applications and various technology platforms. This article explores barriers to such a transformation near-term.


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