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XC018 LP 5V aporc02_5v is a Power-on-Reset (POR) circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.

XC018 LP 3.3V aporc02_3v3 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.

XH018 LP3MOS 1.8V aporc02_1v8 is a Power-on-Reset circuit with hysteresis. Both high and low reset signals are available. Reset signals are generated on power-on and power-off transitions. 40mV (typ) hysteresis for safer operation.

XC10: A_CELLS; A_CELLS_M1. aporc02 is a digital power-on-reset circuit. PORB output is kept low as long as the supply voltage is below the POR threshold voltage. PORB signal is generated on both rising and falling edges of the supply voltage. During power

XC06: A_CELLS. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept high as long as the supply voltage is bellow the high threshold

XH035: A_CELLS. For MOS module only. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is b

XT06 aporc02 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on both the rising and failing edge of the supply voltage. During power-on, POR outputs is kept high as long as the supply voltage is below the threshold voltage.

XC018 LP 5V aporc01_5v is a dynamic Power-on-Reset (POR) circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low.

XC018 LP 3.3V aporc01_3v3 is a dynamic power-on-reset circuit (POR). The cell is suitable for applicaitons where low consumption is important.

XC10: A_CELLS; A_CELLS_M1. aporc01 is a digital power-on-reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. After the threshold has been reached, the POR signals turns low. A delay of

XC06: A_CELLS. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is bellow the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay of few microse

XH035: A_CELLS. For MOS module only. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay

XT06 aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low.

XC10: A_CELLS; A_CELLS_M1. apogc01 is a general purpose, power good detector. A power good signal (active high) is generated as long as the supply voltage at the VDDA pin lies within the 4.5V - 5.5V limits. When the supply voltage is beyond the either low

XC06: A_CELLS_HV. aopac15 is a high-voltage, internally-compensated CMOS OpAmp with NMOS input stage and bipolar emitter-follower output. The incorporated level shifters allow the EN and ENB inputs to be controlled by 5V circuitry.

XC06: A_CELLS_HV. aopac14 is a high-voltage (V_DD up to 10V), low-power, internally-compensated CMOS OpAmp with NMOS input stage.

XC06: A_CELLS_HV. aopac13 is a high-voltage (V_DD up to 10V), low-power, internally-compensated CMOS OpAmp with PMOS input stage.

XH018 LP3MOS 1.8V aopac12_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 3.8MHz.

XC06: A_CELLS. aopac12 is a low-power, internally compensated CMOS OpAmp with N-MOS input stage and P-MOS source follower at the output stage.

XH035: A_CELLS. For MOS module only. aopac12 is an internally compensated CMOS differential input - differential output (DIDO) operational amplifier with P-MOS input stage and rail-to-rail output stages.

XT06 aopac12 is a low-power, internally compensated CMOS OpAmp with N-MOS input stage and P-MOS source follower output stage.

XH018 LP3MOS 1.8V aopac11_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 1.5MHz.

XC06: A_CELLS. aopac11 is a low-power, internally compensated CMOS OpAmp with P-MOS input stage and N-MOS source follower at the output stage.

XT06 aopac11 is a low-power, internally compensated CMOS OpAmp with P-MOS input stage and N-MOS source follower output stage.

XH018 LP3MOS 1.8V aopac10_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 382kHz.

XB06: A_CELLS. aopac10 is an internal frequency-compensated CMOS operational amplifier with rail-to-rail input stage and rail-to-rail output stage.

XC06: A_CELLS. aopac10 is a fast internally compensated CMOS OpAmp with P-MOS input stage and N-MOS source follower at the output stage.

XT06 aopac10 is a fast internally compensated CMOS OpAMp with P-MOS input stage and N-MOS source follower output stage.

XC018 LP 3.3V aopac09_3v3 is a general purpose internally compensated PMOS input, rail-to-rail output CMOS operational amplifier (OpAmp).

XH018 LP3MOS 1.8V aopac09_1v8 is a general purpose internally compensated CMOS OpAmp with NMOS native input stage and rail-to-rail output stage. This cell provides typical value of gain bandwidth 162kHz.