IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
OEIC_Sensitive Optical Receiver Channel
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. OEIC_Sensitive is a sensitive DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.

DPIN Integrated Photodiode
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. DPIN_5050 and DPIN_50100 are fast photodiodes with a vertical PIN structure optimized forred light (660nm).

aopac01 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: A_CELLS. aopac01 is a low power internal frequency-compensated CMOS operational amplifier with pmos input stage

aopac02 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac02 is an internal frequency-compensated CMOS operational amplifier with p-mos input stage

aopac03 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac03 is a fast internal frequency-compensated CMOS operational amplifier with p-mos input stage

aopac05 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac05 is a low power internal frequency-compensated CMOS operational amplifier with nmos input stage

aopac06 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac06 is an internal frequency-compensated CMOS operational amplifier with n-mos input stage

aopac07 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac07 is a fast internal frequency-compensated CMOS operational amplifier with n-mos input stage.

aopac09 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac09 is an internal frequency-compensated CMOS operational amplifier with p-mos input stage and rail-to-rail output stage.

aopac10 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac10 is an internal frequency-compensated CMOS operational amplifier with rail-to-rail input stage and rail-to-rail output stage.

acmpc01 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc01 is a low-power two-stage CMOS comparator with n-mos input stage and a CMOS-output stage.

acmpc03 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc03 is a low-power two-stage CMOS comparator with n-mos input stage and a CMOS-output stage.

acmpc04 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc04 is a two-stage CMOS comparator with p-mos input stage and a CMOS-output stage.

acmpc06 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc06 is a two-stage CMOS comparator with p-mos input stage and a CMOS-output stage.

acmpc10 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc10 is a CMOS comparator with rail-to-rail input stage and rail-to-rail output stage.

acmpc11 Comparators
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. acmpc11 is low offset CMOS comparator with rail-to-rail input stage and rail-to-rail output stage.

abgpc01 Bandgaps
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abgpc01 is a Brokaw, general-purpose bandgap reference source with high resistive poly resistor. 

abgpc03 Bandgaps
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abgpc03 is a badgap reference with high resistive poly resistor.

abiac01 Bias
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abiac01 is a bias voltage source (VBP1, VBN1) which needs a bandgap cell for biasing.

abiac02 Bias
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abiac02 is a bias voltage source (VBP2, VBN2) which needs a bandgap cell for biasing.

abiac03 Bias
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abiac03 is a bias voltage source (VBP3, VBN3) which needs a bandgap cell for biasing.

ADC10 ADC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. ADC10 is a 10-bit analog-to-digital converter which utilizes successive approximation technique.

ADC8 ADC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. ADC8 is a 8-bit analog-to-digital converter which utilizes successive-approximation technique.

DAC10 DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC10 is a 10-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recommended at the

DAC8 DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC8 is a 8-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recommended at the ou

DAC8rs DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC8rs is a 8-bit digital-to-analog converter. The architecture is based on a resistor divider. The output impedance is code dependent.

DAC6rs DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC6rs is a 6-bit digital-to-analog converter. The architecture is based on a resistor divider. The output impedance is code dependent.

ADC12DR ADC
A3PICs GmbH
0.60 µm
XB06
PT
GDSII

The ADC12DR is a SAR-based low-power ADC with a 12bit resolution. Its fully differential input stage features a rail-to-rail input range. At a sampling rate of 2MS/s a power consumption of only 10mW is attained applying a 5V power suppl

abiac01_3v3 Bias
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V abiac01_3v3 is a general purpose bias cell. The circuit forces a current of 200nA (approx.) to flow through PMOS with W/L ratio of 8µm/10µm and NMOS with W/L ratio of 4µm/20µm.

abiac02_3v3 Bias
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V abiac02_3v3 is a general purpose bias cell. The circuit forces a current of 2µA (approx.) to flow through PMOS with W/L ratio of 10µm/4µm and NMOS with W/L ratio od 6µm/12µm.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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