IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
QCDAC4_35X DAC
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Resistive String architecture.

QCOP4_35X Operational Amplifier
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Operational Amplifier Cell with P-Channel Inputs

QCOP5_35X Operational Amplifier
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Reference Amplifier

QCPOR4_35X Power on Reset
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Power On Reset cell

QCADB5_35X Other
QualCore Logic, Inc.
0.35 μm
XH035
PT
GDSII
Schematic

Connectivity IP. This is a product chip.

DAC-7bit-0.6u DAC
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS, output to pos rail

DC-DC Converter DC/DC Converters
Ridgetop Group
0.60 µm
XC06
ID
GDSII

Ultra high efficiency programmable output voltage over wide input voltage range, buck/boost. Input: 1.5V - 15V. Output 2V-6V

Comparator 0.6u Comparators
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Ultra Low Power, Wide Supply Range, CMOS

BGR 0.6u Bandgaps
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS

PWM Other
Ridgetop Group
0.35 μm
XH035
ID
GDSII

250kHz PWM for DC-DC converters

High V Input Cell Other
Ridgetop Group
0.35 μm
XH035
ID
GDSII

High Voltage Input for input voltages up to 100V

Sub 1dB LNA+mixer LNA
Mixer
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

LNA  and optional mixer based on XH035 process. Measured noise figure below 1dB including mixer. Described in a paper on the web site.  The techniques are readily applied to other processes.

Low Power DDS Other
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

Novel aproach to Direct Digital Synthesis, using a voltage-ladder reference. Accuracy is achieved by using a full resistor ladder array, so bit size equivalent to 12 bits has been shown. Prototypes using an 8 bit system are available on

Analogue SSB Chip Other
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

Very low power (3V, 25uA) 90 degree analogue phase shifter for SSB encoding/decoding. A full description is on the web site, with all measurements.

SA00AH8A00 ADC
Sony LSI Design Inc.
0.35 μm
XH035
ID
GDSII

SA00AH8A00 is a subranging 8-bit high-speed 50MS/s Analog-to-Digital Converter(ADC) for video band and disk servo use.

SA00AH8B00 ADC
Sony LSI Design Inc.
0.35 μm
XH035
ID
GDSII

SA00AH8B00 is a subranging  8-bit low-power 25MS/s Analog-to-Digital Converter(ADC) for disk servo use.

SA00PFC000 PLL
Sony LSI Design Inc.
0.35 μm
XH035
ID
GDSII

SA00PFC000 is a PLL with internal loop filter. Wide output clock freq. range : 10MHz~200MHz. Wide input clock freq. range : 2MHz~50MHz

SA00PFC010 PLL
Sony LSI Design Inc.
0.35 μm
XH035
ID
GDSII

SA00PFC010 is a PLL with internal loop filter. Wide output clock freq. range : 10MHz~160MHz. Wide input clock freq. range : 2.5MHz~6MHz.

SA00DJAA00 DAC
Sony LSI Design Inc.
0.35 μm
XH035
ID
GDSII

SA00DJAA00 is a high-speed  50MS/s Digital-to-Analog Converter(DAC) for video band use.

VREG1_8 Voltage Regulator
Suter IC-Design AG
0.18 μm
XC018
MP
GDSII
Schematic

Low power voltage regulator for 1.8V logic, requires only an external capacitor, available for XC018/XH018 MOS3LP and MOS5LP, different option available on request.

XTAL5M Crystal Oscillators
Suter IC-Design AG
0.18 μm
XC018
MP
GDSII
Schematic

Low power crystal oscillator for resonator with fast start-up, available for XC018/XH018 MOS3LP, including pads, different pads on request.

aopac01 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library

XC10: A_CELLS; A_CELLS_M1. aopac01 is an internally compensated general purpose OpAmp with P-MOS input and common-source output stage.

aopac02 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac02 is an internally compensated rail-to-rail input/output OpAmp.

aopac03 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac03 is an internally compensated general purpose OpAmp with N-MOS input and bipolar pnp output stage.

aopac04 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac04 is a internally compensated general purpose OpAmp with P-MOS input stage.

aopac05 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac05 is a fast internally compensated OpAmp with P-MOS input stage.

aopac06 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac06 is a high-gain, high load current CMOS OpAmp with N-MOS input and rail-to-trail output stage.

aopac07 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. aopac07 is a general purpose internally compensated OpAmp with P-MOS input and source follower output stage.

acmpc01 Comparators
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. acmpc01 is a general purpose voltage comparator with P-MOS input and hysteresis.

acmpc03 Comparators
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. acmpc03 is a general purpose, low-consumption voltage comparator with N-MOS input.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 31 to 60 out of 370

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