adrvc01 * Driver X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. adrvc01 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output. The rising slope of the output signal can be controlled by means of a bias current.
atmpc01 * Miscellaneous X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. atmpc01 is a high-temperature detector. An OVERT output signal (active low) is generated when the chip temperature rises above 140 °C (approx.).
atmpc02 * Miscellaneous X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. atmpc02 is a high-temperature detector. An OVERT output signal (active low) is generated when the chip temperature rises above 160 °C (approx.).
HT_ADC1 ADC IMMS GmbH 1.00 µm XI10 PT GDSII This IP is a cyclic ADC based on RSD algorithm usable as core for embedded applications. The special advantage of this type of ADC is the reduced complexity of hardware resp. layout area because of the reuse of the main stages for each bit. Up to 13 bit o
SUPI4 Soft IP MAZeT Gmbh All Geometries All Processes VS VHDL Interbus Slave Controller Version 4. Visit MAZeT website for datasheet.
EnDAT2.2 Soft IP MAZeT Gmbh All Geometries All Processes VS VHDL Sensor Interface used in positioning systems. Visit MAZet website for datasheet.
IPMS_430 Microprocessor Fraunhofer IPMS All Geometries All Processes PT VHDL 16 Bit Microcontroller
The core IPMS_430 is compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features are
- 16 bit Risc CPU
- 7 address modes for source operands
- 4 a
IPMS_16CXX Microprocessor Fraunhofer IPMS All Geometries All Processes PT VHDL 8 Bit Microprocessor.
The core IPMS_16CXX realizes a to the PIC 16CXX-family of the firm Microchip compatible 8-bit microcontroller Important features are:
- 8-bit arithmetic (addition, subtraction, logical operations, bit manipulation)
- to 64 k i
IPMS_16550 Soft IP Fraunhofer IPMS All Geometries All Processes PT VHDL The UART-core IPMS_16550 realize the functionality of an serial interface.
Features:
Data rates, data formats and interrupt events are programmable
compatible to UART 16550
high flexibility in different uses
IPMS_AES Soft IP Fraunhofer IPMS All Geometries All Processes VS VHDL Cryptographie core according to AES standard
Features
High processing speed of 100 Mbit / s (128 bit key, 25 MHz).
Same speed for coding and decoding.
Key widths of 128, 192 and 256 bit are implemented
120 kGates.
IPMS_CAN Soft IP Fraunhofer IPMS All Geometries All Processes PT VHDL CAN-Controller
Features
implementation of the Basic CAN specification
no generated Overload Frames
receiving and transmitting of both identifiers (CAN specification 2.0B)
programmable data rate up to 1 Mbit/s
programmable
IPMS_DES Other Fraunhofer IPMS All Geometries All Processes VS VHDL Cryptographic Processor Core for the DES Algorithm
The hardware realizes a flexible DES core to encrypt and decrypt data with high speed. The encryption /decryption of a 64 bit data set takes 16 clock periods.
IPMS_ECC Soft IP Fraunhofer IPMS All Geometries All Processes VS VHDL Processor core for Elliptic Curve Cryptography
IEEE-Standard 1076-1993 compliant synthesizable VHDL model for utiliza¬tion as macro cell in ASIC and FPGA designs
Diffie-Hellman key exchange proto¬col exists
Implementation of other proto¬cols based o
IPMS_IIC Other Fraunhofer IPMS All Geometries All Processes PT VHDL The core realized the I²C-bus protocol
Features:
Master and receive mode realized
Bus node address and data transmission rate are programmable
8 Bit data interface to the controller
All I²C function are implemented
Core is multimasterable
IPMS_IRHSP Soft IP Fraunhofer IPMS All Geometries All Processes VS VHDL IrDA Hight Speed Protocl Stack
Features:
Complete IrDA protocol stack (IrPHY, Framer, IrLAP, IrLMP, IAS, TinyTP, IrCOMM, IrOBEX)
Primary and secondary function (scalable)
Data rates from 9.6 kbit / s - 16 Mbit / s (scalable)
IR remote control functio
IPMS_LIN Soft IP Fraunhofer IPMS All Geometries All Processes PT VHDL LIN (Local Interconnect Network) is a serial communication protocol
Features
Support of LIN specification 2.0
Programmable data rate between 1 Kbit/s and 20 Kbit/s
4 MHz clock frequency
8-byte data buffer
8-bit host controller interface
Support of
IPMS_RSA Soft IP Fraunhofer IPMS All Geometries All Processes VS Verilog Cryptographic Processor Core for Public Key En¬cryption
processor core for modulo n multiplication and exponentiation (RSA) with high speed and high bit sizes
Data rates (for a 1024 bit system at 25 MHz clock frequency)
1024 bit RSA up to 10 kbit/s
IMMSD2026A Soft IP IMMS GmbH All Geometries All Processes PT Verilog The soft IP module D2026A implements a SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. The SENT protocol constitutes a low-cost alternative to the LIN and CAN commu
