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XH018 LP3MOS 1.8V arcoc01_1v8 is a robust 1MHz low-power RC oscillator with internal R and C. The cell features low power consumption. Frequency independent on load capacity.

XH018 LP3MOS 1.8V arcoc02_1v8 is a robust 1MHz RC oscillator with internal R and C. Frequency independent on load capacity.

XH018 LP3MOS 1.8V arcoc01_1v8 is a robust 5MHz low-power RC oscillator with internal R and C. The cell features low power consumption. Frequency independent on load capacity.

XH018 LP3MOS 1.8V arcoc051_1v8 is a robust 5MHz RC oscillator with internal R and C. Frequency independent on load capacity.

XH018 LP3MOS 1.8V arcoc06_1v8 is a robust 5MHz low-voltage RC oscillator with internal R and C. The cell operates with V_DD down to 1.2V. Frequency independent on load capacity.

XH018 LP3MOS 1.8V arcoc07_1v8 is a robust 10MHz RC oscillator with internal R and C. Frequency independent on load capacity.

XH018 LP3MOS 1.8V arcoc08_1v8 is a robust 20MHzRC oscillator with internal R and C. Frequency independent on load capacity.

XH018 LP3MOS 1.8V arcoc09_1v8 is a robust 40MHz RC oscillator with internal R and C. Frequency independent on load capacity.

 XH018 LP3MOS 1.8V arcoc10_1v8 is a robust 100kHz RC oscillator with internal R and C. Frequency independent on load capacity.

XH018 LP3MOS 1.8V arcoc11_1v8 is a robust 200kHz RC oscillator with internal R and C. Frequency independent on load capacity.

XH018 LP3MOS 1.8V arcoc12_1v8 is a robust 10kHz RC oscillator with internal R and C. Frequency independent on load capacity.

XH018 LP3MOS 3.3V abiac01_3v3 is a general purpose bias cell. the circuit provides bias voltages so that a current of 200nA (approx.) to flow through PMOS with W/L ration of 8µm/10µm and NMOS with W/L ratio of 4µm/20µm.

XH018 LP3MOS 3.3V abiac02_3v3 is a general purpose bias cell. the circuit provides bias voltages so that a current of 2µA (approx.) to flow through PMOS with W/L ration of 10µm/4µm and NMOS with W/L ratio of 6µm/12µm.

XH018 LP3MOS 3.3V abiac03_3v3 is a general purpose bias cell. the circuit provides bias voltages so that a current of 10µA (approx.) to flow through PMOS with W/L ration of 24µm/2µm and NMOS with W/L ratio of 14µm/6µm.

XH018 LP3MOS 3.3V acsoc01_3v3 is a compact general purpose current source. The circuit has four outputs that drive currents of 200nA each. The current outputs can be connected in parallel in order to obtain bigger output currents in the 200nA-800nA range.

XH018 LP3MOS 3.3V acsoc02_3v3 is a compact general purpose current source. The circuit has four outputs that drive currents of 1µA; 2µA; 4µA; and 8µA, respectively.

XH018 LP3MOS 3.3V abgpc01_3v3 is a general purpose bandgap reference with N-well resistors. This bandgap cell also provides reference voltage for some bias cells.

XH018 LP3MOS 3.3V abgpc02_3v3 is a general purpose bandgap reference with polysilicon resistors.

XH018 LP3MOS 3.3V abgpc04_3v3 is a low-voltage bandgap reference with N-well resistors.

XH018 LP3MOS 3.3V aopac01_3v3 is a general purpose internally compensated CMOS OpAmp with N-MOS input stage and rail-to-rail output stage. The speed, gain bandwidth, and the power consumption of the amplifier are set by means of a bias current.

XH018 LP3MOS 3.3V aopac02_3v3 is a general purpose internally compensated CMOS OpAmp with P-MOS input stage and rail-to-rail output stage. The speed, gain bandwidth, and the power consumption of the amplifier are set by means of a bias current.

XH018 LP3MOS 3.3V aopac03_3v3 is a general purpose internally compensated CMOS OpAmp with N-MOS input stage and rail-to-rail output stage. The speed, gain bandwidth, and the power consumption of the amplifier are set by means of a bias current.

XH018 LP3MOS 3.3V aopac04_3v3 is a general purpose internally compensated CMOS OpAmp with P-MOS input stage and rail-to-rail output stage. The speed, gain bandwidth, and the power consumption of the amplifier are set by means of a bias current.

This IP is a cyclic ADC based on RSD algorithm usable as core for embedded applications. The special advantage of this type of ADC is the reduced complexity of hardware resp. layout area because of the reuse of the main stages for each bit. Up to 13 bit o

DC/DC regulator.

DC/DC Buck Regulator with 0% to 100% duty cycle.

Bandgap Voltage Reference and Current Bias Cell.

Current Reference and Current Biasing Cell.

Comparator Cell with N-Channel Inputs

Resistive String architecture.