aregc01 * Voltage Regulator X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. aregc01 is a 5V / 3.3V positive voltage linear regulator for up to 10 mA load current.
aregc02 * Voltage Regulator X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. aregc02 is a 2.4V / 3.3V positive voltage switching regulator for on-chip loads and up to 10 mA load current.
AV2102 600mA Buck Voltage Regulator Aivaka 0.60 µm XC06 PT GDSII DC/DC regulator.
aregc01 * Voltage Regulator X-FAB 0.35 μm XH035 PT Layout XH035: A_CELLS_HV. For MOS module only. aregc01 is a 5V/3.3V linear voltage regulator for up to 20mA load current. The regulator is powered viz its high voltage input.
aregc02 * Voltage Regulator X-FAB 0.35 μm XH035 PT Schematic XH035: A_CELLS_HV. For MOS module only. aregc02 is a 12V/3.3V linear voltage regulator for up to 20mA load current. The regulator is powered via its high-voltage input.
AV2110 600mA Buck Voltage Regulator Aivaka 0.60 µm XC06 PT GDSII DC/DC Buck Regulator with 0% to 100% duty cycle.
QCBGB10_35X Voltage Regulator QualCore Logic, Inc. 0.35 μm XH035 MP GDSII Bandgap Voltage Reference and Current Bias Cell.
VREG1_8 Voltage Regulator Suter IC-Design AG 0.18 μm XC018 MP GDSII Low power voltage regulator for 1.8V logic, requires only an external capacitor, available for XC018/XH018 MOS3LP and MOS5LP, different option available on request.
aregc01_3v3 * Voltage Regulator X-FAB 0.18 μm XC018 PT Layout XC01801_3v3 is a 3.3V/1.8V linear voltage regulator for up to 20mA load current and internal bandgap reference. The regulator is implimented as a macro cell that fits into the core-limited I/O ring.
CM1112ae Voltage Regulator chipus 0.35 μm XH035 MP GDSII General purpose linear voltage regulator. The circuit generates a 3.3V output voltage from an unregulated input voltage ranging from 5V to 30V. It features short circuit protection and 5mA output current capability.
LCVCO2 * VCO X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LCVCO_CELLS. LCVCO2 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It is based on a cross-coupled bipolar transistor pair. It contains AC-coupled varactors and a special circuit technique for maintaining the D
LCVCO3 * VCO X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other
RINGVCO1 * VCO X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_VCO_CELLS. RINGVCO1 is a fully integrated VCO. It should be biased by the RF bias cell. It consists of a ringoscillator that is tuned by switching the delay chain between 2 and 4 delay stages. The transition between the two borders i
avcoc01_3v3 * VCO X-FAB 0.18 μm XC018 PT Layout XC018 LP 3.3V avcoc01_3v3 is a voltage controlled oscillator (VCO).
SUPI4 Soft IP MAZeT Gmbh All Geometries All Processes VS VHDL Interbus Slave Controller Version 4. Visit MAZeT website for datasheet.
EnDAT2.2 Soft IP MAZeT Gmbh All Geometries All Processes VS VHDL Sensor Interface used in positioning systems. Visit MAZet website for datasheet.
IPMS_430 Microprocessor Fraunhofer IPMS All Geometries All Processes PT VHDL 16 Bit Microcontroller
The core IPMS_430 is compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features are
- 16 bit Risc CPU
- 7 address modes for source operands
- 4 a
IPMS_16CXX Microprocessor Fraunhofer IPMS All Geometries All Processes PT VHDL 8 Bit Microprocessor.
The core IPMS_16CXX realizes a to the PIC 16CXX-family of the firm Microchip compatible 8-bit microcontroller Important features are:
- 8-bit arithmetic (addition, subtraction, logical operations, bit manipulation)
- to 64 k i
IPMS_16550 Soft IP Fraunhofer IPMS All Geometries All Processes PT VHDL The UART-core IPMS_16550 realize the functionality of an serial interface.
Features:
Data rates, data formats and interrupt events are programmable
compatible to UART 16550
high flexibility in different uses
IPMS_AES Soft IP Fraunhofer IPMS All Geometries All Processes VS VHDL Cryptographie core according to AES standard
Features
High processing speed of 100 Mbit / s (128 bit key, 25 MHz).
Same speed for coding and decoding.
Key widths of 128, 192 and 256 bit are implemented
120 kGates.
IPMS_CAN Soft IP Fraunhofer IPMS All Geometries All Processes PT VHDL CAN-Controller
Features
implementation of the Basic CAN specification
no generated Overload Frames
receiving and transmitting of both identifiers (CAN specification 2.0B)
programmable data rate up to 1 Mbit/s
programmable
IPMS_ECC Soft IP Fraunhofer IPMS All Geometries All Processes VS VHDL Processor core for Elliptic Curve Cryptography
IEEE-Standard 1076-1993 compliant synthesizable VHDL model for utiliza¬tion as macro cell in ASIC and FPGA designs
Diffie-Hellman key exchange proto¬col exists
Implementation of other proto¬cols based o
IPMS_IRHSP Soft IP Fraunhofer IPMS All Geometries All Processes VS VHDL IrDA Hight Speed Protocl Stack
Features:
Complete IrDA protocol stack (IrPHY, Framer, IrLAP, IrLMP, IAS, TinyTP, IrCOMM, IrOBEX)
Primary and secondary function (scalable)
Data rates from 9.6 kbit / s - 16 Mbit / s (scalable)
IR remote control functio
IPMS_LIN Soft IP Fraunhofer IPMS All Geometries All Processes PT VHDL LIN (Local Interconnect Network) is a serial communication protocol
Features
Support of LIN specification 2.0
Programmable data rate between 1 Kbit/s and 20 Kbit/s
4 MHz clock frequency
8-byte data buffer
8-bit host controller interface
Support of
IPMS_RSA Soft IP Fraunhofer IPMS All Geometries All Processes VS Verilog Cryptographic Processor Core for Public Key En¬cryption
processor core for modulo n multiplication and exponentiation (RSA) with high speed and high bit sizes
Data rates (for a 1024 bit system at 25 MHz clock frequency)
1024 bit RSA up to 10 kbit/s
IMMSD2026A Soft IP IMMS GmbH All Geometries All Processes PT Verilog The soft IP module D2026A implements a SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. The SENT protocol constitutes a low-cost alternative to the LIN and CAN commu
aporc01 * Power on Reset X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. aporc01 is a digital power-on-reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. After the threshold has been reached, the POR signals turns low. A delay of
aporc02 * Power on Reset X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. aporc02 is a digital power-on-reset circuit. PORB output is kept low as long as the supply voltage is below the POR threshold voltage. PORB signal is generated on both rising and falling edges of the supply voltage. During power
aporc04 * Power on Reset X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. aporc04 is a digital power-on-reset circuit. PORB output is kept low as long as the supply voltage is below the high POR threshold voltage. PORB signal is generated on both rising and falling edges of the supply voltage. During
apogc01 * Power on Reset X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. apogc01 is a general purpose, power good detector. A power good signal (active high) is generated as long as the supply voltage at the VDDA pin lies within the 4.5V - 5.5V limits. When the supply voltage is beyond the either low
