SA00PFC010 PLL Sony LSI Design Inc. 0.35 μm XH035 ID GDSII SA00PFC010 is a PLL with internal loop filter. Wide output clock freq. range : 10MHz～160MHz. Wide input clock freq. range : 2.5MHz～6MHz.
PA * Power Amplifiers X-FAB 0.60 µm XB06 PT Schematic XB06: LNA library: RF_PA_CELLS. PA is a non-linear Power Amplifier that is intended for the transmission of ASK and FSK signals. Its output power level can be digitally controlled in 4 steps. It should be biased by the RF bias cell.
aporc01 * Power on Reset X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. aporc01 is a digital power-on-reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. After the threshold has been reached, the POR signals turns low. A delay of
aporc02 * Power on Reset X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. aporc02 is a digital power-on-reset circuit. PORB output is kept low as long as the supply voltage is below the POR threshold voltage. PORB signal is generated on both rising and falling edges of the supply voltage. During power
aporc04 * Power on Reset X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. aporc04 is a digital power-on-reset circuit. PORB output is kept low as long as the supply voltage is below the high POR threshold voltage. PORB signal is generated on both rising and falling edges of the supply voltage. During
apogc01 * Power on Reset X-FAB 1.00 µm XC10 PT Analog Library XC10: A_CELLS; A_CELLS_M1. apogc01 is a general purpose, power good detector. A power good signal (active high) is generated as long as the supply voltage at the VDDA pin lies within the 4.5V - 5.5V limits. When the supply voltage is beyond the either low
aporc01 * Power on Reset X-FAB 0.60 µm XC06 PT Layout XC06: A_CELLS. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is bellow the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay of few microse
aporc02 * Power on Reset X-FAB 0.60 µm XC06 PT Layout XC06: A_CELLS. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept high as long as the supply voltage is bellow the high threshold
aporc03 * Power on Reset X-FAB 0.60 µm XC06 PT Layout XC06: A_CELLS. aporc03 is a Power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept low as long as the supply voltage is bellow the threshold voltage. When the high
aporc01 * Power on Reset X-FAB 0.35 μm XH035 PT Layout XH035: A_CELLS. For MOS module only. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay
aporc02 * Power on Reset X-FAB 0.35 μm XH035 PT Layout XH035: A_CELLS. For MOS module only. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is b
aporc03 * Power on Reset X-FAB 0.35 μm XH035 PT Layout XH035: A_CELLS. For MOS module only. aporc03 is a Power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is below the threshold v
aporc01_5v * Power on Reset X-FAB 0.18 μm XC018 PT Layout XC018 LP 5V aporc01_5v is a dynamic Power-on-Reset (POR) circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low.
aporc02_5v * Power on Reset X-FAB 0.18 μm XC018 PT Layout XC018 LP 5V aporc02_5v is a Power-on-Reset (POR) circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.
aporc03_5v * Power on Reset X-FAB 0.18 μm XC018 PT Layout XC018 LP 5V aporc03_5v is a Power-on-Reset (POR) circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.
aporc01 * Power on Reset X-FAB 0.60 µm XT06 PT Layout XT06 aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low.
aporc02 * Power on Reset X-FAB 0.60 µm XT06 PT Layout XT06 aporc02 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on both the rising and failing edge of the supply voltage. During power-on, POR outputs is kept high as long as the supply voltage is below the threshold voltage.
aporc03 * Power on Reset X-FAB 0.60 µm XT06 Layout XT06 aporc03 is a Power-on-Rest circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept high as long as the supply voltage is below the high threshold.
QCPOR4_35X Power on Reset QualCore Logic, Inc. 0.35 μm XH035 MP GDSII Power On Reset cell
aporc01_3v3 * Power on Reset X-FAB 0.18 μm XC018 PT Layout XC018 LP 3.3V aporc01_3v3 is a dynamic power-on-reset circuit (POR). The cell is suitable for applicaitons where low consumption is important.
aporc02_3v3 * Power on Reset X-FAB 0.18 μm XC018 PT Layout XC018 LP 3.3V aporc02_3v3 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.
aporc03_3v3 * Power on Reset X-FAB 0.18 μm XC018 PT Layout XC018 LP 3.3V aporc03_3v3 is a Power-on-Rest circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.
aporc03_5v * Power on Reset X-FAB 0.18 μm XC018 PT Analog Library XC018 LP 5V aporc03_5v is a power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.
CM1412ae Power on Reset chipus 0.35 μm XH035 MP GDSII 2Low consumption Power-On Reset (POR) core. The core has a voltage sense (configurable 0.9V - 5.5V), an internal current bias circuit and two configurable assertion delays (default are > 1μs and > 20μs). A configurable hysteresis (default 100mV).
SUPI4 Soft IP MAZeT Gmbh All Geometries All Processes VS VHDL Interbus Slave Controller Version 4. Visit MAZeT website for datasheet.
EnDAT2.2 Soft IP MAZeT Gmbh All Geometries All Processes VS VHDL Sensor Interface used in positioning systems. Visit MAZet website for datasheet.
IPMS_16550 Soft IP Fraunhofer IPMS All Geometries All Processes PT VHDL The UART-core IPMS_16550 realize the functionality of an serial interface.
Features:
Data rates, data formats and interrupt events are programmable
compatible to UART 16550
high flexibility in different uses
IPMS_AES Soft IP Fraunhofer IPMS All Geometries All Processes VS VHDL Cryptographie core according to AES standard
Features
High processing speed of 100 Mbit / s (128 bit key, 25 MHz).
Same speed for coding and decoding.
Key widths of 128, 192 and 256 bit are implemented
120 kGates.
IPMS_CAN Soft IP Fraunhofer IPMS All Geometries All Processes PT VHDL CAN-Controller
Features
implementation of the Basic CAN specification
no generated Overload Frames
receiving and transmitting of both identifiers (CAN specification 2.0B)
programmable data rate up to 1 Mbit/s
programmable
IPMS_ECC Soft IP Fraunhofer IPMS All Geometries All Processes VS VHDL Processor core for Elliptic Curve Cryptography
IEEE-Standard 1076-1993 compliant synthesizable VHDL model for utiliza¬tion as macro cell in ASIC and FPGA designs
Diffie-Hellman key exchange proto¬col exists
Implementation of other proto¬cols based o
