IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
acmpc03_3v3 Comparators
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V acmpc03_3v3 is a rail-to-rail input, current-programmable CMOS comparator. The speed and power consumption of the comparator can be controlled by means of the bias current through the IBN input.

acmpc01_5v Comparators
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 5V acmpc01_5v is a low-power current-programmable CMOS comparator with hysteresis. The input stage is P-MOS differential pair. The speed and power consumption of the comparator can be controlled by means of the bias current through the IBN input.

acmpc02_5v Comparators
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 5V acmpc02_5v is a low-power current-programmable CMOS comparator with hysteresis. The input stage is N-MOS differential pair. The speed and power consumption of the comparator can be controlled by means of the bias current through the IBN input.

acmpc01 Comparators
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 acmpc01 is a low-power CMOS comparator with N-MOS input stage.

acmpc02 Comparators
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 acmpc02 is a low-power CMOS comparator with P-MOS input stage.

acmpc03 Comparators
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 acmpc03 is a fast CMOS comparator with N-MOS input stage. A 15mV (typ.) hysteresis is intentionally introduced to ensure proper operation.

acmpc04 Comparators
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 acmpc04 is a fast CMOS comparator with P-MOS input stage. A 15mV (typ.) hysteresis is intentionally introduced to ensure proper operation.

acmpc06 Comparators
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 acmpc06 is a fast rail-to-rail CMOS voltage comparator.

QCCMP4_35X Comparators
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Comparator Cell with N-Channel Inputs

acmpc03_5v Comparators
X-FAB
0.18 μm
XC018
PT
Analog Library
Layout
Schematic

XC018 LP 5V acmpc03_5v is a rail-to-rail input, current-programmable CMOS comparator.

Comparator 0.6u Comparators
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Ultra Low Power, Wide Supply Range, CMOS

acmpc01_3v3 Comparators
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V acmpc01_3v3 is a low-power current-programmable CMOS comparator with hysteresis. The input stage is P-MOS differential pair.

acmpc02_3v3 Comparators
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V acmpc02_3v3 is a low-power current-programmable CMOS comparator with hysteresis. The input stage is N-MOS differential pair.

acmpc03_3v3 Comparators
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V acmpc03_3v3 is a low-power current-programmable CMOS comparator.

achpc01 Charge Pumps
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. achpc01 is doubling charge pump 5V to 8.75V.

achpc02 Charge Pumps
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. achpc02 is a 4-stage Dickson charge pump originally designed for EEPROM.

achpc01 Charge Pumps
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. achpc01 is a doubling charge pump 3.3V -> 5.7V. All capacitors are internal.

achpc01 Charge Pumps
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 achpc01 is a doubling charge pump 3.3V => 5.6V.

abiac01 Bias
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. abiac01 is a general purpose VTH - based current reference. The circuit forces a current of 2.4μA (approx.) to flow through P- or N-MOS transistor with a W/L ratio of 10μm/6μm.

abiac02 Bias
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. abiac02 is a general purpose weak inversion bias cell. The circuit forces a current of 250nA (approx.) to flow through P- or N-MOS transistors with a W/L ratio of 10μm/10μm.

BIAS Bias
X-FAB
0.60 µm
XB06
PT
Verilog
Schematic
Layout
Analog Library

XB06: LNA library: RF_BIAS_CELLS. BIAS is a bias cell intended for use with various RF building blocks. It is designed as a bandgap reference as well as voltage-to-current converter. Current biasing is preferable because of the higher immunity to interfer

abiac01 Bias
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abiac01 is a bias voltage source (VBP1, VBN1) which needs a bandgap cell for biasing.

abiac02 Bias
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abiac02 is a bias voltage source (VBP2, VBN2) which needs a bandgap cell for biasing.

abiac03 Bias
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. abiac03 is a bias voltage source (VBP3, VBN3) which needs a bandgap cell for biasing.

abiac07 Bias
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. abiac07 is a high-voltage bias cell. The circuit forces a current of 2µA (approx.) to flow through pghv PMOS with W/L ratio of 10µm/10µm and nmv NMOS with W/L ratio of 10µm/12µm.

abiac08 Bias
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. abiac08 is a high-voltage bias cell. THe circuit forces a current of 2µA (approx.) to flow through pgmv PMOS with W/L ratio of 10µm/10µm and nhv NMOS with W/L ratio od 10µm/12µm. The cell features low-cost process option and is a co

abiac01 Bias
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. abiac01 is a general purpose bias cell. The circuit forces a current of 2µA (approx.) to flow through PMOS with W/L ratio of 6µm/6µm and NMOS with W/L ration of 6µm/6µm.

abiac02 Bias
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. abiac02 is a general purpose VTH-based bias cell, a plain substitute for abiac01. The circuit forces a current of 2µA (approx.) to flow through PMOS with W/L ratio of 6µm/6µm and NMOS with W/L ration

abiac03 Bias
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. abiac03 is a general purpose weak inversion bias cell. The circuit forces a current of 200nA (approx.) to flow through PMOS with W/L ratio of 6µm/12µm and NMOS with W?L ration of 6µm/20µm.

acsoc01 Bias
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. acsoc01 is a general purpose current source. The circuit drives a current of 2µA (approx.) at each of its outputs.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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