IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
arcoc06 Oscillator
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 arcoc06 is a 1MHz adjustable, current balancing RC oscillator with internal R and C.

arcoc07 Oscillator
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 arcoc07 is a 10kHz low-power oscillator with internal R and C.

arcoc08 Oscillator
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 arcoc08 is a 10MHz low-power oscillator with internal R and C.

arcoc09 Oscillator
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 arcoc09 is a 20MHz low-power oscillator with internal R and C.

axtoc01 Crystal Oscillators
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 axtoc01 is a 32kHz crystal oscillator for 3.5 to 5.5V supply voltage range. An external quartz has to be connected to XTALIN and XTALOUT pins.

axtoc02 Crystal Oscillators
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 axtoc02 is a 1...4MHz crystal oscillator for supply voltage range from 3.5 to 5.5V. An external quartz crystal as to be connected to XTALIN and XTALOUT pins.

axtoc03 Crystal Oscillators
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 axtoc03 is a 1...6MHz crystal oscillator for supply voltage range from 3.3 to 5.5V. An external quartz crstal has to be connected to XTALIN and XTALOUT pins.

aporc01 Power on Reset
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low.

aporc02 Power on Reset
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 aporc02 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on both the rising and failing edge of the supply voltage. During power-on, POR outputs is kept high as long as the supply voltage is below the threshold voltage.

achpc01 Charge Pumps
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 achpc01 is a doubling charge pump 3.3V => 5.6V.

AV2102 600mA Buck Voltage Regulator
Aivaka
0.60 µm
XC06
PT
GDSII

DC/DC regulator.

AV2110 600mA Buck Voltage Regulator
Aivaka
0.60 µm
XC06
PT
GDSII

DC/DC Buck Regulator with 0% to 100% duty cycle.

QCADB5_35X Other
QualCore Logic, Inc.
0.35 μm
XH035
PT
GDSII
Schematic

Connectivity IP. This is a product chip.

AR32X3A ADC
Archband Labs Inc.
0.25 μm
FC025
PT
GDSII

AR32X3A is a 16-bit ADC for measurement purpose in 0.25µm node.

AR25X01 Other
Archband Labs Inc.
0.25 μm
FC025
PT
GDSII

AR25X01 is a 35mA LDO with the capless option in 0.25µm node

Sub 1dB LNA+mixer LNA
Mixer
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

LNA  and optional mixer based on XH035 process. Measured noise figure below 1dB including mixer. Described in a paper on the web site.  The techniques are readily applied to other processes.

Low Power DDS Other
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

Novel aproach to Direct Digital Synthesis, using a voltage-ladder reference. Accuracy is achieved by using a full resistor ladder array, so bit size equivalent to 12 bits has been shown. Prototypes using an 8 bit system are available on

Analogue SSB Chip Other
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

Very low power (3V, 25uA) 90 degree analogue phase shifter for SSB encoding/decoding. A full description is on the web site, with all measurements.

IPMS_430 Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

Compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features:
- 16 bit Risc CPU
- 7 address modes for source operands
- several low power features

IPMS_16CXX Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

8 Bit Microprocessor. The core IPMS_16CXX is a 8-bit microcontroller compatible to PIC 16CXX-family from Microchip.

IPMS_CAN_FD Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

IPMS_CAN is a CAN bus controller that performs serial communication according to the CAN 2.0B and the CAN FD specification.It is compatible to ISO CAN FD andthe non-ISO (Bosch) CAN FD standard and has extended time stamp and time trigger capabilities.

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol used in low cost automotive networks. It enables cost efficient bus communication for applications where the bandwidth of CAN is not required. Support of LIN specification 2.2A

IMMS SENT Transmitter Soft IP
IMMS GmbH
All Geometries
All Processes
PT
Verilog

Silicon-proven Verilog implementation of a flexible configurable SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. Up to 16-bit data from two independent sensors.

abgpc01_3v3 Bandgaps
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V abgpc01 is a general purpose low-power bandgap reference with N-well resistors.

abgpc02_3v3 Bandgaps
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V abgpc02 is a general purpose low-power bandgap reference with rnp1 resistors

abgpc03_3V3 Bandgaps
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V abgpc03 is a low-voltage bandgap reference with N-well resistors.

aopac03_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac03_3v3 is a general purpose internally compensated rail-to-rail input, rail-to-rail output CMOS operational amplifier (OpAmp). The speed, gain bandwidth, and the power consumption of the amplifier are set by means of a bias curren

aopac06_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac06_3v3 is a general purpose internally compensated rail-to-rail input, rail-to-rail output CMOS operational amplifier (OpAmp).

aopac07_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac07_3v3 is a general purpose internally compensated rail-to-rail input, railt-to-rail ouput CMOS operational ampl;ifier (OpAmp).

aopac08_3v3 Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V aopac08_3v3 is a general internally compensated NMOS input, rail-to-rail output CMOS operational amplifier (OpAmp).

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 241 to 270 out of 369

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