axtoc02 *
Crystal Oscillators
X-FAB
0.35 μm
XH035
PT
Layout Schematic Analog Library
XH035: A_CELLS. For MOS module only. axtoc02 is a robust 32,768kHz crystal oscillatior for supply voltage range from 2.4 to 2.6V. An external quartz crystal is required.
aporc01 *
Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout Schematic Analog Library
XH035: A_CELLS. For MOS module only. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay
aporc02 *
Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout Schematic Analog Library
XH035: A_CELLS. For MOS module only. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is b
aporc03 *
Power on Reset
X-FAB
0.35 μm
XH035
PT
Layout Schematic Analog Library
XH035: A_CELLS. For MOS module only. aporc03 is a Power-on-Reset circuit. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output follows the supply voltage as long as it is below the threshold v
aregc01 *
Voltage Regulator
X-FAB
0.35 μm
XH035
PT
Layout Schematic Analog Library
XH035: A_CELLS_HV. For MOS module only. aregc01 is a 5V/3.3V linear voltage regulator for up to 20mA load current. The regulator is powered viz its high voltage input.
abiac02_3v3 *
Bias
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 3.3V abiac02_3v3 is a general purpose bias cell. The circuit forces a current of 2µA (approx.) to flow through PMOS with W/L ratio of 10µm/4µm and NMOS with W/L ratio od 6µm/12µm.
abiac01_3v3 *
Bias
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 3.3V abiac01_3v3 is a general purpose bias cell. The circuit forces a current of 200nA (approx.) to flow through PMOS with W/L ratio of 8µm/10µm and NMOS with W/L ratio of 4µm/20µm.
DIV32 *
Divider
X-FAB
0.35 μm
XH035
PT
Layout Schematic Analog Library
XH035: DIVIDER Library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed ratio of 32. It should be biased by the RF bias cell.
acmpc01_3v3 *
Comparators
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 3.3V acmpc01_3v3 is a low-power current-programmable CMOS comparator with hysteresis. The input stage is P-MOS differential pair. The speed and power consumption of the comparator can be controlled by means of the bias current through the IBN inp
acmpc02_3v3 *
Comparators
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 3.3V acmpc02_3v3 is a low-power current-programmable CMOS comparator with hysteresis. The input stage is N-MOS differential pair.
acmpc03_3v3 *
Comparators
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 3.3V acmpc03_3v3 is a rail-to-rail input, current-programmable CMOS comparator. The speed and power consumption of the comparator can be controlled by means of the bias current through the IBN input.
aadcc01_3v3 *
ADC
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 3.3V aadcc01_3v3 is a 10-bit successive approximation Analog-to-Digital converter (ADC). The ADC operates with a single 3.3V power supply and an external voltage reference.
adacc01_3v3 *
DAC
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 3.3V adacc01_3v3 is a 10-bit voltage-scaling (potentionetric) Digital-to-Analog converter (DAC). The adacc01 DAC operates with a single 3.3V power supply and external reference voltage.
abiac06_5v *
Bias
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V abiac06_5v is a general purpose bias cell. The circuit forces a current of 10µA (approx.) to flow through PMOS with W/L ratio of 24µm/3µm and NMOS with W/L ratio of 10µm/4µm.
abiac07_5v *
Bias
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V abiac07_5v is a general purpose bias cell. The circuit forces a current of 2µA (approx.) to flow through PMOS with W/L ratio of 10µm/6µm and NMOS with W/L ratio of 10µm/12µm.
acsoc01_5v *
Current Source
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5v acsoc01_5v is a compact general purpose current source. The circuit has four outputs that drive currents of 1µA, 2µA, 4µA, and 8µA, respectively.
acsoc02_5v *
Current Source
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5v acsoc02_5v is a compact general purpose current source. The circuit has four outputs that drive currents of 200nA each.
aopac01_5v *
Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V aopac01_5v is a general purpose internally compensated CMOS OpAmp with N-MOS input stage and rail-to-rail output stage. The speed, gain bandwidth, and the power consumption of the amplifier are set by means of bias current.
aopac02_5v*
Operational Amplifier
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V aopac02_5v is a general purpose internally compensated CMOS OpAmp withP-MOS input stage and rail-to-rail output stage. The speed, gain bandwidth, and the power consumption of the amplifier are set by means of bias current.
acmpc01_5v *
Comparators
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V acmpc01_5v is a low-power current-programmable CMOS comparator with hysteresis. The input stage is P-MOS differential pair. The speed and power consumption of the comparator can be controlled by means of the bias current through the IBN input.
acmpc02_5v *
Comparators
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V acmpc02_5v is a low-power current-programmable CMOS comparator with hysteresis. The input stage is N-MOS differential pair. The speed and power consumption of the comparator can be controlled by means of the bias current through the IBN input.
arcoc01_5v *
Oscillator
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V arcoc01_5v is a robust 100kHz RC oscillator with internal R and C. The cell features very low temperature coefficient of clock frequency and low power consumption.
arcoc02_5v *
Oscillator
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V arcoc02_5v is a robust 1MHz RC oscillator with internal R and C. The cell features very low temperature coefficient of clock frequency and low power consumption.
arcoc03_5v *
Oscillator
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V arcoc03_5v is an adjustable 100kHz, current-balancing RC oscillator with internal R and C. The very low temperature coefficient of clock frequency combined with trimming inputs, very low power consumption and compact size make the cell ideal s
arcoc04_5v *
Oscillator
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V arcoc04_5v is an adjustable 1MHz, current-balancing RC oscillator with internal R and C. The very low temperature coefficient of the clock frequency combined with trimming inputs, very low power consumption and compact size make the cell ideal
aporc01_5v *
Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V aporc01_5v is a dynamic Power-on-Reset (POR) circuit. During power-on, POR output follows the supply voltage as long as it is below the threshold voltage. When the threshold voltage is reached, the POR signal turns low.
aporc02_5v *
Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V aporc02_5v is a Power-on-Reset (POR) circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage.
aporc03_5v *
Power on Reset
X-FAB
0.18 μm
XC018
PT
Layout Schematic Analog Library
XC018 LP 5V aporc03_5v is a Power-on-Reset (POR) circuit. Reset signals are generated on both the rising and falling edge of the supply voltage.
aopac01 *
Operational Amplifier
X-FAB
0.60 µm
XT06
PT
Layout Schematic Analog Library
XT06 aopac01 is a general purpose internally compensated CMOS OpAmp with P-MOS input stage and source follower output stage.
aopac02 *
Operational Amplifier
X-FAB
0.60 µm
XT06
PT
Layout Schematic Analog Library
XT06 aopac02 is a fast internally compensated CMOS OpAmp with N-MOS input stage and rail-to-rail output stage.