IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
adacc02 DAC
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. adacc02 is a 8-bit R-2R digital-to-analog converter (DAC). The DAC operates with a single 5V power supply and external reference voltage.

adacc03 DAC
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. adacc03 is a 8-bit voltage-scaling (potentiometric) digital-to-analog converter (DAC). The adacc03 DAC operates with a single 5V power supply and external reference voltage.

adacc02 DAC
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: A_CELLS. For MOS module only. adacc02 is a bit-bit voltage-scaling (potentiometric) Digital-to-Analog converter (DAC). The DAC operates with a single 3.3V power supply and external reference voltage.

adacc01_3v3 DAC
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 3.3V adacc01_3v3 is a 10-bit voltage-scaling (potentionetric) Digital-to-Analog converter (DAC). The adacc01 DAC operates with a single 3.3V power supply and external reference voltage.

adacc01 DAC
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 adacc01 is a 10-bit voltage-scaling (potentiometric) digital-to-analog converter (DAC). The adacc01 DAC operates with a single 5V power supply and external reference voltage.

adacc02 DAC
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06 adacc02 is an 8-bit R-2R digital-to-analog converter (DAC). The adacc02 DAC operates with a single 5V power supply and external reference voltage.

adacc03 DAC
X-FAB
0.60 µm
XT06
PT
Layout
Schematic
Analog Library

XT06

QCDAC4_35X DAC
QualCore Logic, Inc.
0.35 μm
XH035
MP
GDSII
Schematic

Resistive String architecture.

SA00DJAA00 DAC
Sony LSI Design Inc.
0.35 μm
XH035
ID
GDSII

SA00DJAA00 is a high-speed  50MS/s Digital-to-Analog Converter(DAC) for video band use.

DAC-7bit-0.6u DAC
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS, output to pos rail

adacc01_3v3 DAC
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V adacc01_3v3 is a 10-bit voltage-scaling (potentiometric) Digital-to-Analog converter. The adacc01 DAC operates with a single 3.3V analog power supply; a 1.8V digital power supply and an external reference voltage.

DC-DC Converter DC/DC Converters
Ridgetop Group
0.60 µm
XC06
ID
GDSII

Ultra high efficiency programmable output voltage over wide input voltage range, buck/boost. Input: 1.5V - 15V. Output 2V-6V

DIV32 Divider
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed divider ratio of 32. It should be biased by the RF bias cell.

DIV32 Divider
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: DIVIDER Library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed ratio of 32. It should be biased by the RF bias cell.

adrvc01 Driver
X-FAB
1.00 µm
XC10
PT
Analog Library
Layout
Schematic

XC10: A_CELLS; A_CELLS_M1. adrvc01 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output. The rising slope of the output signal can be controlled by means of a bias current.

adrvc01 Driver
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. adrvc01 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output (high-side switch). High input voltage makes the output go low (connected to ground). The rising slope of the output signal c

adrvc02 Driver
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. adrvc02 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output (low-side switch). High input voltage makes the output go low (connected to ground).

adrvc03 Driver
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. adrvc03 is a driver circuit for external loads (relays, LEDs, etc). The circuit features NMOS open-drain output (high-side switch). High input voltage makes the output go low (connected to ground). The rising slope of the output signal c

adrvc02 Driver
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. adrvc02 is a driver circuit for external loads (relays, LEDs, etc). The circuit features PNOS open-drain output (high-side switch). The layout of adrvc02 makes it easy to incorporate in the flat IO ring.

adrvc03 Driver
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. adrvc03 is a driver circuit for external loads (realys, LEDs, etc). The circuit features NMOS open-drain output (low-side switch). The layout of adrvc03 makes it easy to incorporate in the flat IO ring.

DPIN Integrated Photodiode
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. DPIN_5050 and DPIN_50100 are fast photodiodes with a vertical PIN structure optimized forred light (660nm).

LNA1 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA 1 is a low noise amplifier. It shoud be biased by the RF bias cell.

LNA2 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA2 is a low noise amplifier. It should be biased by the RF bias cell

LNA3 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA3 is a low noise amplifier with on-chip inductor. It should be biased by the RF bias cell.

LNA1 LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA1 is a broadband low noise amplifier. It should be bieased by the RF bias cell.

LNA2 LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA2 is a narrowband low noise amplifier. It should be biased by the RF bias cell.

Sub 1dB LNA+mixer LNA
Mixer
Saul Research
0.35 μm
XH035
PT
GDSII
Schematic

LNA  and optional mixer based on XH035 process. Measured noise figure below 1dB including mixer. Described in a paper on the web site.  The techniques are readily applied to other processes.

IPMS_430 Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL

16 Bit Microcontroller

The core IPMS_430 is compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features are

- 16 bit Risc CPU

- 7 address modes for source operands

- 4 a

IPMS_16CXX Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL

8 Bit Microprocessor.

The core IPMS_16CXX realizes a to the PIC 16CXX-family of the firm Microchip compatible 8-bit microcontroller Important features are:

- 8-bit arithmetic (addition, subtraction, logical operations, bit manipulation)

- to 64 k i

MIXER Mixer
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_MIXER_CELLS. MIXER is a down conversion mixer based on a Gilbert cell topology. It should be biased by the RF bias cell.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 151 to 180 out of 368

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